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16.3 Flash Memory Status Register (FSTR)
The flash memory status register (FSTR) indicates the operation status of the flash
memory.
This register also controls interrupts to the CPU and writing to the flash memory.
Only the CPU can access this register. Even if a writer is provided, it cannot access
this register.
Do not access this register with Read Modify Write instructions.
Flash Memory Status Register (FSTR)
The flash memory status register (FSTR) has the following structure:
bit (during byte access)
address 007C0h
initial value
Read/Write
[bit 7] INTE (INTerrupt Enable)
The INTE bit controls interrupts generated by the termination of the automatic algorithm in
flash memory (for a write/erase operation etc.).
This bit is initialized to "0" during a reset. Read and write operations are enabled.
0: disables issuing interrupts at termination of the automatic algorithm.
(This is the initial value)
1: enables issuing interrupts at termination of the automatic algorithm.
[bit 6] RDYINT (ReaDY INTerrupt)
The PDYINT bit is set to "1" when the automatic algorithm (for a write/erase operation etc.) in
flash memory terminates.
When bit 7 (INT = "1") enables interrupt output and this bit (bit 6) is set to "1", an interrupt
request for terminating the automatic algorithm is generated.
After a reset, the bit is initialized "0". Read/Write operations for this bit are enabled. However,
only write operations with the value "0" are valid: even when a write operation attempts to set
"1", the value of this bit remains unchanged.
Cause for clearing: Clear is performed by writing "0" through an instruction.
Cause for setting: The bit is set by termination of the automatic algorithm (when the rising
edge of the RDY/BUSYX signal is detected).
[bit 5] WE (Write Enable)
The WE bit controls writing data and commands to the flash memory in CPU mode.
When this bit is "0", writing data and commands to the flash memory becomes invalid. Data
from flash memory is read in 32-bit access mode.
7
6
5
WE
INTE RDYINT
"0"
"0"
"0"
R/W
R/W
R/W
16.3 Flash Memory Status Register (FSTR)
4
3
2
RDY
Undefined Undefined Undefined Undefined
R
1
0
"0"
"0"
R/W
355
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