CHAPTER 4 BUS INTERFACE
Connection Example of DRAM Device
•
DRAM: 2CAS/1WE, page size 512, × 16-bit product
•
Bus width: 16 bits
•
Number of banks: 2 (areas 4 and 5)
Figure 4.16-20 Example of Connection between MB91F109 and Two 16-Bit Output DRAMs (16-Bit Data
(Area4 RAS) RAS0
(Area4 CASL) CSOL
(Area4 CASH) CS0H
(Area4 WE)
(Area5 RAS) RAS1
(Area5 CASL) CS1L
(Area5 CASH) CS1H
(Area5 WE)
(A00 not
connected)
158
This LSI
DW0X
DW1X
RDX
A09-01
D31-16
Bus)
Area 4 DRAM
RAS
UCAS
LCAS
WE
OE
A8-A0
D16-D1
Area 5 DRAM
RAS
UCAS
LCAS
WE
OE
A8-A0
D16-D1