Serial Status Register (Ssr) - Fujitsu MB91F109 FR30 Hardware Manual

10.5 Serial Status Register (SSR)

The serial status register (SSR) consists of flags that show the UART operating status.
Configuration of Serial Status Register (SSR)
The configuration of the serial status register (SSR) is shown below:
SSR 00001C
Address:000020
000024
Bit Function of Serial Status Register (SSR)
[bit 7] PE (Parity Error)
This bit is an interrupt request flag that is set when a parity error is detected for received
data.
To clear the flag once it is set, set the REC bit (bit 10) of the SCR register to "0".
When this bit is set, SIDR data is invalidated.
0: No parity error is present. (Initial value)
1: A parity error is present.
[bit 6] ORE (Over Run Error)
This bit is an interrupt request flag that is set when an overrun is detected for received data.
To clear the flag once it is set, set the REC bit of the SCR register to "0".
When this bit is set, SIDR data is invalidated.
0: No overrun is present. (Initial value)
1: An overrun is present.
[bit 5] FRE (FRaming Error)
This bit is an interrupt request flag that is set when a framing error is detected for received
data.
To clear the flag once it is set, set the REC bit of the SCR register to "0".
When this bit is set, SIDR data is invalidated.
0: No framing error is present. (Initial value)
1: A framing error is present.
7 6 5
H
PE ORE FRE RDRF TDRE
H
H
R R R
4 3 2
RIE
R R R/W
10.5 Serial Status Register (SSR)
1 0
Initial value
TIE 00001-00
R/W
B
253