Figure 4.17-28 Example 4 Of Dram Interface Timing Chart In High-Speed Page Mode - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE
Combination of high-speed page mode and basic bus cycle

Figure 4.17-28 Example 4 of DRAM Interface Timing Chart in High-Speed Page Mode

Q4
CLK
A24-00 CS4X col.adr CS2X basic bus CS2X basic bus
D31-24
D23-16
CS2X
CS4X
RDX
WR0X
CS4:RAS
CS4:CASL
CS4:CASH
CS4:WE
CS4 high-speed page
[Explanation of operation]
• Even if the CS area switches and another CS area is accessed, RAS remains at "L" in high-
speed page mode.
184
Q5 BA1 BA2
Read Write
Read Write
CS2 basic bus
BA1 BA2 Idle
Read
Read
Q4 Q5 Q4
CS4X col.adr CS4X col.adr
Read
Read
CS4 high-speed page
Q5
Read
Read