Dram Interface In High-Speed; Figure 4.17-25 Example 1 Of Dram Interface Timing Chart In High-Speed Page Mode; Figure 4.17-26 Example 2 Of Dram Interface Timing Chart In High-Speed Page Mode - Fujitsu MB91F109 FR30 Hardware Manual

CHAPTER 4 BUS INTERFACE
4.17.13 DRAM Interface in High-Speed Page Mode
This section provides DRAM interface operation timing charts in high-speed page
mode.
DRAM Interface Timing Charts in High-Speed Page Mode
Read cycle, bus width: 16 bits, access: words

Figure 4.17-25 Example 1 of DRAM Interface Timing Chart in High-Speed Page Mode

Q1
CLK
1) 1CAS/2WE
A24-00 X
D31-24
D23-16
RAS
CAS
WEL
WEH
RDX
[Explanation of operation]
• Read control is performed with only the CAS control signals (including CASL and CASH)
while RAS is lowered to "L", and "H" of WE (including WEL and WEH) is held.
• Column addresses are output in Q4 and Q5 cycles.
Write cycle, bus width: 16 bits, access: words

Figure 4.17-26 Example 2 of DRAM Interface Timing Chart in High-Speed Page Mode

Q1
CLK
2) 2CAS/1WE
A24-00 X
D31-24
D23-16
RAS
CASL
CASH
WE
RDX
182
Q2 Q3 Q4
#0 row.adr. #0 col.adr
Usual DRAM bus cycle
Q2 Q3 Q4
#0 row.adr. #0 col.adr
#0
#1
Usual DRAM bus cycle
Q5 Q4 Q5
#2 col.adr
#0 #2
#1 #3
High-speed page High-speed page High-speed page
Q5 Q4 Q5
#2 col.adr
#2
#3
High-speed page High-speed page High-speed page
Q4 Q5 Q4
#4 col.adr #6 col.adr
#4 #6
#5 #7
Q4 Q5 Q4
#4 col.adr #6 col.adr
#4 #6
#5 #7
Q5
Q5