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BV44.
IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold Reset
Problem:
IA32_FEATURE_CONTROL MSR (3Ah) may have random values after RESET (including
the reserved and Lock bits), and the read-modify-write of the reserved bits and/or the
Lock bit being incorrectly set may cause an unexpected GP fault.
Implication:
Due to this erratum, an unexpected GP fault may occur and BIOS may not complete
initialization.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV45.
DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP
SS is Followed by a REP MOVSB or STOSB
Problem:
Normally, data breakpoints matches that occur on a MOV SS, r/m or POP SS will not
cause a debug exception immediately after MOV/POP SS but will be delayed until the
instruction boundary following the next instruction is reached. After the debug
exception occurs, DR6.B0-B3 bits will contain information about data breakpoints
matched during the MOV/POP SS as well as breakpoints detected by the following
instruction. Due to this erratum, DR6.B0-B3 bits may not contain information about
data breakpoints matched during the MOV/POP SS when the following instruction is
either an REP MOVSB or REP STOSB.
Implication:
When this erratum occurs, DR6 may not contain information about all breakpoints
matched. This erratum will not be observed under the recommended usage of the MOV
SS,r/m or POP SS instructions (i.e., following them only with an instruction that writes
(E/R)SP).
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV46.
Setting Hardware Autonomous Speed Disable Configuration Bit Will
Block Initial Speed Upgrade
Problem:
The PCI Express* Base Specification Revision 3.0 states that the Hardware
Autonomous Speed Disable bit (Link Control Register 2, bit 5) does not block the initial
transition to the highest supported common link speed. Setting this bit will block all
autonomous speed changes.
Implication:
Due to this erratum, if the Hardware Autonomous Speed Disable bit is set, a given PCIe
link may remain at 2.5 GT/s transfer rate. This erratum has not been observed with any
commercially available add-in cards.
Workaround:
It is possible for software to initiate a directed speed change.
Status:
For the steppings affected, see the Summary Tables of Changes.
BV47.
LTR Message is Not Treated as an Unsupported Request
Problem:
The PCIe* root port does not support LTR (Latency Tolerance Reporting) capability.
However, a received LTR message is not treated as a UR (Unsupported Request).
Implication:
Due to this erratum, an LTR message does not generate a UR error.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
Specification Update
33
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