Introduction; Terminology - Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet

Introduction

1 Introduction
The Intel
quad processor Q6000 sequence are the first desktop quad-core processors that
combine the performance and power efficiencies of four low-power microarchitecture
cores to enable a new level of multi-tasking, multi-media, and gaming experiences.
They are 64-bit processors that maintain compatibility with IA-32 software.
The processors use Flip-Chip Land Grid Array (FC-LGA6) package technology, and plug
into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the
LGA775 socket. The processors are based on 65 nm process technology.
Note: In this document the Intel
and Intel
"processor."
Note: In this document the Intel
®
Intel Core™2 quad processor Q6600 and Q6700. The Intel
core processor QX6000 sequence refers to the Intel
processors QX6700, QX6800, and QX6850.
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2) and
Streaming SIMD Extensions 3 (SSE3). The processor supports several advanced
technologies including Execute Disable Bit, Intel
Virtualization Technology (VT).
The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol
like the Intel
of address and data to improve performance by transferring data four times per bus
clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address
bus can deliver addresses two times per bus clock and is referred to as a "double-
clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 10.7 GB/s.
The processor uses some of the infrastructure already enabled by the
775_VR_CONFIG_05 platforms including heatsink, heatsink retention mechanism, and
socket. Supported platforms may need to be refreshed to ensure the correct voltage
regulation (VRD11) and PECI support is enabled. Manufacturability is a high priority;
hence, mechanical assembly may be completed from the top of the baseboard and
should not require any special tooling.
The processor includes an address bus power-down capability that removes power from
the address and data signals when the FSB is not in use. This feature is always enabled
on the processor.
1.1

Terminology

A '#' symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested. Conversely, when NMI is high, a nonmaskable interrupt has
occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the '#' symbol implies
that the signal is inverted. For example, D[3:0] = 'HLHL' refers to a hex 'A', and
D[3:0]# = 'LHLH' also refers to a hex 'A' (H= High logic level, L= Low logic level).
Datasheet
®
Core™2 Extreme quad-core processor QX6000 sequence and Intel
®
Core™2 Extreme quad-core processor QX6000 sequence
®
Core™2 quad processor Q6000 sequence are referred to simply as
®
Core™2 quad-core processor Q6000 sequence refers to the
® ®
Pentium 4 processor. The FSB uses Source-Synchronous Transfer (SST)
®
Core™2 Extreme quad-
®
Core™2 Extreme quad-core
®
64 architecture, and Intel
®
Core™2
®
9