Intel BX80562QX6700 - Core 2 Extreme 2.66 GHz Processor Datasheet page 68

Table 25. Signal Description (Sheet 7 of 9)
Name
RS[2:0]#
SKTOCC#
SMI#
STPCLK#
TCK
TDI, TDI_M
TDO, TDO_M
TESTHI[13,
11:10,7:0]
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Type
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
Input
must connect the appropriate pins/lands of all processor FSB
agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the
Output processor. System board designers may use this signal to determine
if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
Input
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop Grant state. The processor issues a Stop
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
Input The processor continues to snoop bus transactions and service
interrupts while in Stop Grant state. When STPCLK# is de-asserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
Input
(also known as the Test Access Port).
TDI and TDI_M (Test Data In) transfer serial test data into the
processor cores. TDI and TDI_M provide the serial input needed for
Input
JTAG specification support. TDI connects to core 0. TDI_M connects
to core 1.
TDO and TDO_M (Test Data Out) transfer serial test data out of the
processor cores. TDO and TDI_M provide the serial output needed
Output
for JTAG specification support. TDO connects to core 1. TDO_M
connects to core 0.
TESTHI[13,11:10,7:0] must be connected to the processor's
appropriate power source (refer to VTT_OUT_LEFT and
Input
VTT_OUT_RIGHT signal description) through a resistor for proper
processor operation. See
Land Listing and Signal Descriptions
Description
Section 2.4 for more details.
Datasheet