Tir6: Interrupt Unmask Register 1; Tir7: Interrupt Unmask Register 2 - AMD Am79C930 Preliminary Manual

TIR6: Interrupt Unmask Register 1

Interrupt Unmask Register 1. Each bit in this register will
unmask the corresponding interrupt of Interrupt Regis-
ter 1 (TIR4) when the unmask bit is set to 1. When the
Bit Name
7 CHBSYCU
6 ANTSWU
5 MOREINTU
4 TXCNTUN
3 TXDONE
2 CRCSU
1 SDSNTU
0 TXFBNU

TIR7: Interrupt Unmask Register 2

Interrupt Unmask Register 2.
Each bit in this register will unmask the corresponding
interrupt of Interrupt Register 2 (TIR5) when the unmask
Bit Name
7 RXCNTU
6 CRC8GU
5 CRC32GU
4 RXFORU
3 RXFBAU
2 SDFU
1 BCFU
0 ALOKIU
P R E L I M I N A R Y
(Generated from the internal signal stop_d, which indicates that an-
tenna diversity operation has selected an antenna.) Assertion of
ALOKI indicates the cessation of antenna diversity activity so that
the incoming network signal can be tracked and decoded by the
DPLL. ALOKI will be set to a 1 by the Am79C930 device when the
conditions for stopping the antenna diversity switching as set up in
the Baud Detect Circuit Control Registers, TCR17, TCR18, TCR20,
TCR21, TCR22, and TCR23, and the RSSI Limit Register TIR28,
and the CCA, and Antenna Diversity Control Register TCR28, have
been met.
Reset Value Description
0 CHBSY Change Interrupt Unmask.
0 Antenna Switch Interrupt Unmask.
0 MOREINT Interrupt Unmask.
0 TX Byte Count Interrupt Unmask.
0 TXDONE Interrupt Unmask.
0 CRC Start Interrupt Unmask.
0 Start of Frame Delimiter Sent Interrupt Unmask.
0 TX FIFO Byte Needed Interrupt Unmask.
Reset Value Description
0 RX Byte Count Interrupt Unmask.
0 CRC8 Good Interrupt Unmask.
0 CRC32 Good Interrupt Unmask.
0 RX FIFO Overrun Interrupt Unmask.
0 RX FIFO Byte Available Interrupt Unmask.
0 Start Delimiter Found Interrupt Unmask.
0 Busy Channel Found Interrupt Unmask.
0 Antenna Lock Interrupt Found Interrupt Unmask.
Am79C930
unmask bit for any interrupt is set to 0, then the bit in the
Interrupt register may still become set, but no interrupt
to the 80188 embedded controller will occur.
bit is set to 1. When the unmask bit for any interrupt is set
to 0, then the bit in the Interrupt register may still become
set, but no interrupt to the 80188 embedded controller
will occur.
AMD
93