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PCMCIA PIN FUNCTION SUMMARY
PCMCIA Pin Summary
No. of
Pins
Pin Name
15
A14–A0
8
D7–D0
1
RESET
1
CE1
1
OE
1
WE
1
REG
1
INPACK
1
WAIT
1
IORD
1
IOWR
1
IREQ
1
STSCHG
1
PCMCIA
1
PWRDWN
17
MA16–0
8
MD7–0
1
FCE
1
SCE
1
XCE
1
MOE
1
MWE
1
TCK
1
TDI
16
P R E L I M I N A R Y
PCMCIA address bus lines
PCMCIA data bus lines
PCMCIA bus RESET line
Card Enable 1—used to enable the D7–0 pins for PCMCIA Read and Write
accesses
Output Enable—used to enable the output drivers of the Am79C930 device for
PCMCIA Read accesses
Write Enable—used to indicate that the current PCMCIA cycle is a write access
REG—used to indicate that the current PCMCIA cycle is to the Attribute
Memory space of the Am79C930 device
Input Acknowledge—used to indicate that the Am79C930 device will respond
to the current I/O read cycle
Wait—used to delay the termination of the current PCMCIA cycle
I/O Read—this signal is asserted by the PCMCIA host system whenever an
I/O read operation occurs
I/O Write—this signal is asserted by the PCMCIA host system whenever an
I/O write operation occurs
Interrupt Request—this line is asserted when the Am79C930 device needs
servicing from the software
Status Change—PCMCIA output used only for WAKEUP signaling
PCMCIA mode—selects PCMCIA or ISA Plug and Play mode
Powerdown—indicates that device is in the power down mode
Memory Address Bus—these lines are used to address locations in the Flash
device, the SRAM device, and an extra peripheral device that are contained
within an Am79C930-based design
Memory Data Bus—these lines are used to write and read data to/from Flash,
SRAM, and/or an extra peripheral device within an Am79C930-based design
Flash Chip Enable—this signal becomes asserted when the Flash device has
been addressed by either the 80188 core of the Am79C930 device or by the
software through the PCMCIA interface
SRAM Chip Enable—this signal becomes asserted when the SRAM device
has been addressed by either the 80188 core of the Am79C930 device or by
the software through the PCMCIA interface
eXtra Chip Enable—this signal becomes asserted when the extra peripheral
device has been addressed by the 80188 core of the Am79C930 device (XCE
is not accessible through the system interface)
Memory Output Enable—this signal becomes asserted during reads of devices
located on the memory interface bus
Memory Write Enable—this signal becomes asserted during writes to devices
located on the memory interface bus
Test Clock—this is the clock signal for IEEE 1149.1 testing
Test Data In—this is the data input signal for IEEE 1149.1 testing
Am79C930
Pin Function
Pin Style
I
TS2
I
I
I
I
I
TS1
TS2
I
PTS3
PTS1
I
TP1
TP1
TS1
TP1
TP1
TP1
TP1
TP1
I
I
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