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PCMCIA I/O READ ACCESS
Parameter
Symbol
Parameter Description
Address setup to IORD
tAVIGL
Address hold from IORD
tIGHAX
REG setup to IORD
tRGLIGL
REG hold from IORD
tIGHRGH
CE setup to IORD
tELIGL
CE hold from IORD
tIGHEH
IORD width
tIGLIGH
INPACK
tIGLIAL
INPACK
tIGHIAH
WAIT
tIGLWTL
WAIT width
tWTLWTH
Data delay from WAIT
tWTHQV
Data enabled from IORD
tIGLQNZ
Data delay from IORD
tIGLQV
Data hold from IORD
tIGHQX
Data disabled from IORD
tIGHQZ
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at "3."
1
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIA READ stycle is being held in wait state.
5
After completion of posted ISA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed
onto memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
P R E L I M I N A R Y
delay from IORD
delay from IORD
delay from IORD
Am79C930
Test Conditions
Notes 1, 2
Note 2
Note 2
AMD
Min
Max
70
20
5
0
5
20
165
0
45
45
35
53 X TCLKIN
0
0
100
0
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
133
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