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ENXCHBSY bit of TCR28 and the CHBSYU bit of
TIR5 and operates independently of the bits in the
table below.
In addition to the functionality listed above, the
USER5/IRQ4/EXTCHBSY pin may be used as the
source for CCA information, instead of relying on the in-
ternal CCA logic of the Am79C930 device. When using
the external CCA information, CCA information from the
internal logic will be unavailable. External CCA informa-
tion will appear in the same register bit locations as in-
ternal CCA information, when enabled, so a change
from internal source to external source will be transpar-
ent to firmware (excepting the necessary change in the
ENXCHBSY bit value).
PCMCIA
ENXCHBSY
Pin
TCR28[5]
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
Pin 98: ACT
The ACT pin may be configured for input or output op-
eration. The output drive may be programmed for totem
pole or open drain operation. ACT pin configuration is
accomplished according to the following table:
ACTEN
ACT
TCR15[1]
TIR0[6]
0
X
1
0
1
1
1
0
1
1
Pin 100: LNK
The LNK pin may be configured for input or output op-
eration. The output drive may be programmed for totem
pole or open drain operation. LNK pin configuration is
accomplished according to the following table:
LNKEN
LNK
TCR13[7]
TIR0[7]
0
X
1
0
1
1
1
0
1
1
P R E L I M I N A R Y
USER5FN
USER5EN
TCR7[5]
TCR15[2]
X
X
0
X
0
X
0
0
0
1
1
0
1
1
X
X
X
0
X
1
ACTDR
ACT Pin
TCR27[3]
Direction
X
I
0
OD
0
OD
1
O
1
O
LNK Pin
LNKDR
TCR27[4]
Direction
X
I
0
OD
0
OD
1
O
1
O
Am79C930
This source of CCA information is controlled by the
ENXCHBSY bit of TCR28. When the ENXCHBSY bit of
TCR28 is set to a 1, then the value of the
USER5/IRQ4/EXTCHBSY pin will be fed directly to the
CHBSYC bit of TIR4, CHBSY bit of TIR26 and the BCF
bit of TIR5. If the CHBSYC interrupt is unmasked, it will
produce an interrupt to the 80188 embedded controller.
If the BCF interrupt is unmasked, it will produce an inter-
rupt to the 80188 embedded controller. Note that setting
the ENXCHBSY bit of TCR28 to a 1 will cause the
USER5/IRQ4/EXTCHBYS pin to function as an input,
regardless of the settings of the other control
bits listed.
IRQ Select
IRQ Type
PnPx70
PnPx71
X
X
4h
2h
4h
1h
4h
X
4h
X
X
X
X
X
X
X
X
X
X
X
Note that a read of the ACT bit (TIR0[6]) will always
give the current ACT pin value, regardless of pin
configuration setting.
ACT Pin
Value
NA
float
reset default condition
LOW
HIGH
LOW
Note that a read of the LNK bit (TIR0[7]) will always
give the current LNK pin value, regardless of pin
configuration setting.
LNK Pin
Value
NA
float
reset default condition
LOW
HIGH
LOW
AMD
USER5/
USER5/
IRQ4
IRQ4
Direction
Pin Data
I
TIR11[5]
O
IRQ4
OD
IRQ4
I
TIR11[5]
O
TIR11[5]
I
TIR11[5]
O
TIR11[5]
I
TIR11[5]
I
TIR11[5]
O
TIR11[5]
37
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