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AMD
PCMCIA I/O WRITE ACCESS
Parameter
Symbol
Parameter Description
Address setup to IOWR
tAVIWL
Address hold from IOWR
tIWHAX
REG setup to IOWR
tRGLIWL
REG hold from IOWR
tIWHRGH
CE setup to IOWR
tELIWL
CE hold from IOWR
tIWHEH
IOWR width
tIWLIWH
WAIT
tIWLWTL
WAIT width
tWTLWTH
IOWR
tWTHIWH
Data setup to IOWR
tDVIWL
Data hold from IOWR
tIWHDX
Notes:
1. The max value for this parameter assumes the following worst case situation:
Value
Worst Case
0
FLASH and SRAM wait states set at "3."
1
Host performs PCMCIA WRITE cycle at same time that Am79C930 embedded 80188 controller begins
instruction fetch cycle to FLASH memory.
2
PCMCIA WRITE cycle is posted internal to Am79C930 device, pending the completion of the embedded 80188
controller access.
3
Host performs PCMCIA READ cycle immediately following completion of PCMCIA WRITE cycle.
4
After completion of first embedded 80188 access to FLASH, posted PCMCIA WRITE executes to SRAM;
PCMCIISA READ stycle is being held in wait state.
5
After completion of posted PCMCIA WRITE cycle, new embedded 80188 access to FLASH begins.
6
After completion of second embedded 80188 access to FLASH, PCMCIA READ cycle is allowed to proceed onto
memory bus to SRAM; host is still held in wait state.
7
At SRAM READ cycle completion, data is delivered to PCMCIA bus and wait state is exited.
2. Parameter is not included in production test.
134
P R E L I M I N A R Y
delay from IOWR
from WAIT
Test Conditions
Notes 1, 2
Am79C930
Min
Max
70
20
5
0
5
20
165
35
53 X TCLKIN
0
60
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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