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AMD
ISA (IEEE P996) Plug and Play Interface — The
Am79C930 device fully supports the ISA Plug and Play
specification, revision 1.0a.
The ISA Plug and Play interface on the Am79C930 de-
vice supports both memory and I/O cycles. The data bus
is 8 bits in width. The total system space required by the
Am79C930 device is 32 Kbytes and 16 bytes of I/O
space. Since all Am79C930-based memory resources
are also mapped into an I/O port, it is possible to operate
a Am79C930-based design with a system memory allo-
cation of 0 bytes.
When the 32K system memory option is selected, the
Am79C930 device uses device select and bank select
bits in the BSS register (SIR1) in order to allow system
access to a total of 256K of Am79C930 memory re-
sources. The total system I/O space required by the
Am79C930 device is 16 bytes. The 40-byte I/O option is
not available in the ISA Plug and Play mode of opera-
tion. The EIOW bit (bit 2 of the BSS register (SIR1)) will
be forced to 0 when the Am79C930 device has been
placed into ISA Plug and Play mode. The I/O space of
the Am79C930 device contains the General Configura-
tion Register, the Bank Switching Select Register, and
the set of 32 TIR registers. Additionally, all Am79C930
resources are accessible through I/O accesses (i.e., all
memory structures are accessible through the Local
Memory Address and Data Ports (SIR2,3,4,5,6,7)).
The Local Memory Address port plus SIR1[5:3] function
together as a pointer to the memory resources of the
Am79C930 device. SIR1[5] determines the device se-
lected (SRAM or Flash) and SIR1[4:3] and LMA[14:0]
supply the address to the selected device whenever the
I/O Data Port is read or written. Whenever any of the
four I/O Data Ports is accessed, then the Local Memory
Address Port value is automatically incremented by a
value of "1."
The Am79C930 device maps 1K–16 bytes of the upper
1K of the 128K of Flash memory space into the ISA Plug
and Play Resource Data structure. (The upper 16 bytes
of this space may not be used for ISA Plug and Play Re-
source Data, since this space is needed to store the first
instructions that will be fetched by the 80188 core follow-
ing the reset operation.) Byte 0 of the Am79C930 de-
vice's Resource Data is mapped to location 1FC00h of
the Flash memory. Reads of the ISA Plug and Play Data
Resource register will automatically access Flash mem-
ory locations in the range 1FC00h through 1FFF0h.
Since all Flash memory locations are always accessible
through ordinary ISA memory accesses, ISA memory
accesses to locations MBA+7C00h – MBA+7FF0h will
sometimes correspond to the same physical locations
as ISA Plug and Play accesses to Resource Data bytes
000h – 3F0h (i.e., the correspondence will occur when
the device and bank select bits of SIR1 are pointing at
the upper quadrant of the 128K Flash memory
address space).
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P R E L I M I N A R Y
When accessing Am79C930 memory resources
through ISA memory cycle accesses, the upper 9 bits of
the ISA memory address will be used to check for a
match of the address range assigned to the Am79C930
device by the Plug and Play configuration program (i.e.,
the Memory Base Address = MBA). (The Plug and Play
configuration program will have written a memory base
address value into the Memory Base Address regis-
ters—Plug and Play ports 40h and 41h—following sys-
tem boot up and auto-configuration.) The ISA Plug and
Play memory base address must be aligned to a 32K
boundary in memory space. This alignment requirement
should be included in the Resource Data that is pro-
grammed into the Flash device and read by the Plug and
Play configuration utility. These conditions must be sat-
isfied, since the Am79C930 device's Bus Interface Unit
will use the upper 9 bits of the ISA memory address to
determine when an address match has been achieved.
When accessing Am79C930 memory resources
through ISA system memory accesses and when the
upper bits of the ISA address are determined to match
the Am79C930 memory space, then the lower memory
addresses at the ISA interface are passed directly to the
memory interface bus, and the Flash Memory Chip En-
able (FCE) or the SRAM Chip Enable (SCE) signal is as-
serted, depending upon the value of SIR1[5]. The upper
two bits of the memory interface bus are set according to
the value of SIR1[4:3]. ISA memory access control sig-
nals (MEMR, MEMW) are automatically translated into
the appropriate memory interface signals (RD, WR).
When accessing Am79C930 I/O resources through ISA
I/O cycle accesses, the upper 8 bits of the ISA system
address will be ignored. Only the lower 16 bits of ad-
dress will be used to check for a match of the address
range assigned to the Am79C930 device by the Plug
and Play configuration program (i.e., the I/O Base Ad-
dress = IOBA). (The Plug and Play configuration pro-
gram will have written an I/O base address value into the
I/O Base Address registers—Plug and Play ports 60h
and 61h—following system boot up and auto-configura-
tion.) The ISA Plug and Play I/O base address must be
aligned to a 16-byte boundary in I/O space. This align-
ment requirement should be included in the Resource
Data I/O Port Descriptor Base Alignment field that is
programmed into the Flash device and read by the Plug
and Play configuration utility. These conditions must be
satisfied for proper operation.
The Am79C930 device fully supports the Plug and Play
Auto-configuration scheme. The Plug and Play
ADDRESS port, WRITE_DATA port and READ_DATA
port are all supported, as well as 19 of the ISA Plug and
Play Registers. For more detail, see the ISA Plug and
Play section.
Am79C930
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