Mir4: Power Down Length Count [22:16] (Pdlc); Mir5: Free Count [7:0] (Fcnt); Mir6: Free Count [15:8] (Fcnt); Mir7: Free Count [23:16] (Fcnt) - AMD Am79C930 Preliminary Manual

AMD
MIR3: Power Down Length Count [15:8] (PDLC)
This register is used to determine the length of power
down cycles. Before execution of the power down se-
quence, the 80188 core must load the PDLC counter.
Bit Name
0 PDLC[15:8]

MIR4: Power Down Length Count [22:16] (PDLC)

This register is used to determine the length of power
down cycles. Before execution of the power down se-
quence, the 80188 core must load the PDLC counter.
Bit Name
7 PERMAREST
6:0 PDLC[22:16]

MIR5: Free Count [7:0] (FCNT)

This register is a read-only register. Do not write to this
register or unexpected consequences will result.
This register gives the value of the lowest byte of the free
running count. The free running count is a 24-bit counter
Bit Name
7:0 FCNT[7:0]

MIR6: Free Count [15:8] (FCNT)

This register gives the value of the lowest byte of the free
running count. The free running count is a 24-bit counter
that uses the 32 kHz clock as its basis. The free running
Bit Name
7:0 FCNT[15:8]

MIR7: Free Count [23:16] (FCNT)

This register gives the value of the lowest byte of the free
running count. The free running count is a 24-bit counter
that uses the 32 kHz clock as its basis. The free running
Bit Name
7:0 FCNT[23:16]
82
P R E L I M I N A R Y
Reset Value Description
00h Middle 8 bits of the length of the power down counter. The resolu-
tion of the power down length counter is in increments of PMX1/2
periods. The nominal PMX1/2 crystal value is 32.768 kHz, resulting
in a resolution of 31.25 s.
Reset Value Description
0 When set to a 1, this bit prevents the normal termination of the
power down sequence, such that the PDLC and PUCT counts are
ignored, and the power down mode is only exited when the
PCMCIA PWRDWN bit is written with a 0, or when the SIR0
DISPWDN bit is written with a 1.
00h Upper 7 bits of the length of the power down counter. The resolution
of the power down length counter is in increments of PMX1/2 peri-
ods. The nominal PMX1/2 crystal value is 32.768 kHz, resulting in a
resolution of 31.25 s.
Reset Value Description
00h Least significant byte of the free running count.
Reset Value Description
00h Middle byte of the free running count.
Reset Value Description
00h Most significant byte of the free running count.
Am79C930
Upon execution of the power down sequence, the PDLC
value will be counted down to zero and the power down
cycle will end.
Upon execution of the power down sequence, the PDLC
value will be counted down to zero and the power down
cycle will end.
that uses the PMX1/2 clock as its basis. The free run-
ning count is reset only when the reset pin is asserted.
Timer resolution is 31.25 s when PMX1/2 has a fre-
quency of 32.768 kHz.
count is reset only when the reset pin is asserted. Timer
resolution is 31.25 s when PMX1/2 has a frequency of
32.768 kHz.
count is reset only when the reset pin is asserted. Timer
resolution is 31.25 s when PMX1/2 has a frequency of
32.768 kHz.