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Serial Host Interface
Characteristics Of The I
generation of the stop event. Handshaking may also be accomplished by use of the
clock synchronizing mechanism. Slave devices can hold the SCL line low, after
receiving and acknowledging a byte, to force the master into a wait state until the
slave device is ready for the next byte transfer. The SHI supports this feature when
operating as a master device and will wait until the slave device releases the SCL line
before proceeding with the data transfer.
2
5.6.2
I
C Data Transfer Formats
2
I
C bus data transfers follow the following format: after the start event, a slave device
address is sent. This address is 7 bits wide, the eighth bit is a data direction bit
(R/W); '0' indicates a transmission (write), and '1' indicates a request for data (read).
A data transfer is always terminated by a stop event generated by the master device.
However, if the master device still wishes to communicate on the bus, it can generate
another start event, and address another slave device without first generating a stop
event (this feature is not supported by the SHI when operating as an I
device). This method is also used to provide indivisible data transfers. Various
combinations of read/write formats are illustrated in Figure 5-10 and Figure 5-11.
S
Slave Address
Start
Bit
Figure 5-10 I
S
Slave Address
Start
Bit
Figure 5-11 I
5-22
2
C Bus
ACK from
Slave Device
0
A
First Data Byte
R/W
2
C Bus Protocol For Host Write Cycle
ACK from
Slave Device
1
A
Data Byte
N = 0 to M
Data Bytes
R/W
2
C Bus Protocol For Host Read Cycle
DSP56012 User's Manual
ACK from
Slave Device
A
Data Byte
N = 0 to M
Data Bytes
ACK from
Master Device
from Master Device
A
Last Data Byte
2
C master
ACK from
Slave Device
A
S, P
Start or
Stop Bit
AA0425
No ACK
1
P
Stop
Bit
AA0426
MOTOROLA
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