Table of Contents
Advertisement
Parallel Host Interface
Host Interface (HI)
Step 2 of HI Port configuration
2. Option 2: Select polling mode for Host-to-DSP communication
Initialize DSP
And HI Port
DMA Off
Bit 5 = 0
Bit 6 = 0
7
6
$0
INIT
HM1
Reserved; write as 0.
Figure 4-22 HI Initialization—Host Side, Polling Mode
Step 2 Of HI Port Configuration
1. Clear Host Command bit (HC):
Bit 7 = 0
7
6
$1
HC
Reserved; write as 0.
2. Option 1: Select Host Vector (HV)
Optional since HV can be set any time before the host command is executed. DSP Interrupt Vector = The
Host vector multiplied by 2. Default (upon DSP reset): HV = $17
The basic data transfer process from the host processor's view (see Figure 4-16
on page 4-40) is for the host to:
1. Assert HOREQ when the HI is ready to transfer data.
2. Assert HACK (if the interface is using HACK).
3. Assert HR/W to select whether this operation will read or write a register.
4. Assert the HI address (HOA2, HOA1, HOA0) to select the register to be read
or written.
4-46
Optional
5
4
3
2
HM0
HF1
HF0
RREQ
Figure 4-23 HI Configuration—Host Side
DSP56012 User's Manual
10
Disable Interrupts
Bit 0 = 0
Bit 1 = 0
1
0
Interrupt Control Register (ICR)
TREQ RREQ
(Read/Write)
0
Command Vector Register (CVR)
(Read/Write)
DSP Interrupt Vector $0034
AA0330k
AA0331k
MOTOROLA
Advertisement
Table of Contents
