Figure 1-1 Dsp56012 Block Diagram - Motorola DSP56012 User Manual

8
15
Parallel
General
Host
Purpose
Interface I/O
(HI)
(GPIO)
24-Bit
DSP56000
Core
Internal
Data
Bus
Switch
TM
OnCE Port
Program
Interrupt
Clock
Controller
PLL
Gen.
3 4
EXTAL
IRQA, IRQB, NMI, RESET
The DSP56000 core is dual-natured in that there are two independent data memory
spaces, two address arithmetic units, and a Data ALU that has two accumulators and
two shifter/limiters. The duality of the architecture makes it easier to write software
for DSP applications. For example, data is naturally partitioned into coefficient and
data spaces for filtering and transformations, and into real and imaginary spaces for
performing complex arithmetic.
Note: Although the DSP56000 core has built-in support for external memory
expansion, the DSP56012 does not implement this function. For DSP56012
applications, external memory expansion is a function of the host processor.
The DSP56000 architecture is especially suited for audio applications since its
arithmetic operations are executed on 24-bit or 48-bit data words. This is a significant
advantage for audio over 16-bit and 32-bit architectures—16-bit DSP architectures
have insufficient precision for CD-quality sound, and while 32-bit DSP architectures
possess the necessary precision, with extra silicon and cost overhead they are not
suitable for high-volume, cost-driven audio applications
MOTOROLA
9 5
Serial Serial Digital
Audio Host Audio
Interface Interface Transmitter
(SAI) (SHI) (DAX)
Address
Generation
Unit
GDB
PDB
XDB
YDB
Program
Decode
Controller Generator
Program Control Unit
4

Figure 1-1 DSP56012 Block Diagram

DSP56012 User's Manual
DSP56012 Architectural Overview
2
Program
Memory
PAB
XAB
YAB
Program
Address
24 24 + 56
Two 56-Bit Accumulators
Overview
X Data
Y Data
Memory Memory
Expansion
Area
Data ALU
56-Bit MAC
16-Bit Bus
24-Bit Bus
1-9