Port B Control (Pbc) Register; Figure 4-4 Port B I/O Pin Control Logic - Motorola DSP56012 User Manual

Parallel Host Interface
Port B Configuration
Port Control
Register Bit
Port B Data (PBD)
Port B
Register (PBDDR) Bit
Registers
Register (PBC) Bit
Port B Input Data Bit
Peripheral
Logic
4.2.1

Port B Control (PBC) Register

The Port B Control (PBC) register determines which set of functions are used with the
external multiplexed pins. As shown in Figure 4-2 on page 4-4, there are three valid
combinations:
• Parallel I/O (default)
• Host Interface
• Host Interface (with HACK as GPIO)
The default setting (BC1:BC0 = 00) defines the pins as GPIO signals. The other
settings must be programmed by writing to the PBC register. Writing a $1 to the
register defines the pins as the HI port. Writing a $2 to the PBC register defines the
pins as an HI port without a HACK signal; the pin used by HACK in the HI is
defined as a GPIO pin (PB14).
4-6
Data Direction
Register Bit
0
0
1
Register Bit
Data Direction
Port B Control
HI Output Data Bit
HI Data Direction Bit
HI Input Data Bit

Figure 4-4 Port B I/O Pin Control Logic

DSP56012 User's Manual
Pin Function
0 Port B Input Pin
1 Port B Output Pin
X HI Function
(GPIO
Position)
Pin
(Input
Position)
AA0310.11
MOTOROLA