Table 4-4 Horeq Pin Definition - Motorola DSP56012 User Manual

Parallel Host Interface
Host Interface (HI)
Using the INIT bit to initialize the HI hardware may or may not be necessary,
depending on the software design of the interface. The type of initialization
performed when the INIT bit is set depends on the state of TREQ and RREQ in the
HI. The INIT command, which is local to the HI, is designed to conveniently
configure the HI into the desired data transfer mode. The commands are described in
the following paragraphs and in Table 4-4. The host sets the INIT bit, which causes
the HI hardware to execute the INIT command. The interface hardware clears the
INIT bit when the command has been executed.
Note: Hardware reset, software reset, individual reset, and Stop clear INIT.
TREQ RREQ
Interrupt Mode (HM1 = 0, HM0 = 0) INIT Execution
0
0
1
1
0
0
1
1
Note: INIT execution always loads the DMA address counter and clears the channel
according to TREQ and RREQ. INIT execution is not affected by HM1 and
HM0.
The internal DMA counter is incremented with each DMA transfer (each HACK
pulse) until it reaches the last data register (RXL or TXL). When the DMA transfer is
completed, the counter is loaded with the value of the HM1 and HM0 bits. When
changing the size of the DMA word (changing HM0 and HM1 in the ICR), the DMA
4-28

Table 4-4 HOREQ Pin Definition

After INIT Execution
0 INIT = 0; Address Counter = 00
1 INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = 00
0 INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = 00
1 INIT = 0; RXDF = 0; HTDE = 1;
TXDE = 1; HRDF = 0; Address
Counter = 00
DMA Mode (HM1 or HM0 = 1) INIT Execution
0 INIT = 0; Address Counter =
HM1, HM0
1 INIT = 0; RXDF = 0; HTDE = 1;
Address Counter = HM1, HM0
0 INIT = 0; TXDE = 1; HRDF = 0;
Address Counter = HM1, HM0
1 Undefined (Illegal)
DSP56012 User's Manual
Transfer
Direction
Initialized
None
DSP to Host
Host to DSP
Host to/from
DSP
None
DSP to Host
Host to DSP
Undefined
MOTOROLA