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4.1
INTRODUCTION
The parallel Host Interface (HI) can serve as an 8-bit, bidirectional parallel port or, as
Port B, a set of General Purpose Input/Output (GPIO) signals (see Figure 4-1). When
configured as the HI, the port provides a convenient connection to another processor.
Port B supports up to fifteen GPIO pins, each pin individually configurable as an
output or an input. This section describes both functions, including examples of how
to configure and use this port.
8
PB0–PB7
PB8
Port B
PB9
I/0
PB10
(15)
PB11
PB12
PB13
PB14
4.2
PORT B CONFIGURATION
Port B functionality is controlled by three memory-mapped registers (see Figure 4-2
on page 4-4) that define the functions associated with fifteen external pins (see
Figure 4-3 on page 4-5). They are:
• Port B Control register (PBC)
• Port B Data Direction Register (PBDDR)
• Port B Data register (PBD)
Figure 4-4 on page 4-6 shows an overview of the Port B control logic.
Note: Because reset clears both the PBC and PBDDR registers, the default function of
the fifteen specified pins following reset is GPIO input.
Note: Circuitry connected to the Port B pins may need external pull-ups until the
pins are configured for operation.
MOTOROLA
Parallel
Interface
Figure 4-1 Port B Interface
DSP56012 User's Manual
Parallel Host Interface
8
H0–H7
HOA0
HOA1
Host
HOA2
HR/W
HEN
HOREQ
HACK
Introduction
4-3
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