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The process to execute an HC (see Figure 4-28) is as follows:
1. The host processor writes the CVR with the desired HV (the HV is the DSP's
interrupt vector (IV) location divided by two, i.e., if HV = $17, IV = $34).
2. The HC bit is then set.
3. The HCP bit in the HSR is set when the HC bit is set.
4. If the HCIE bit in the HCR has been set by the DSP, the HC interrupt
processing will start. The HV is multiplied by 2 and the result is used by the
DSP as the interrupt vector.
5. When the HC interrupt is acknowledged, the HC bit (and therefore the HCP
bit) is cleared by the HC logic. HC can be read by the host processor as a status
bit to determine when the command is accepted. Similarly, the HCP bit can be
read by the DSP CPU to determine if an HC is pending.
;****************************************
; MAIN PROGRAM... receive data from host
;****************************************
ORG
P:$80
MOVE
#0,R0
MOVE
#3,M0
MOVEP
#1,X:PBC
MOVEP
#0,X:HCR
MOVEP
#$0C00,X:IPR
MOVE
#0,SR
JCLR
#3,X:HSR,*
MOVEP
#$1,X:HGR
*
JMP
Figure 4-28 Receive Data from Host—Main Program
;************************************
; Receive from Host Interrupt Routine
;************************************
MOVEP
X:HORX,X:(R0)+;Receive data.
RTI
END
Figure 4-29 Receive Data from Host Interrupt Routine
To guarantee a stable interrupt vector, write HV only when HC is clear. The HC bit
and HV can be written simultaneously. The host processor can clear the HC bit to
cancel a host command at any time before the DSP interrupt is accepted. Although
the HV can be programmed to any interrupt vector, it is not recommended that
HV = 0 (RESET) be used because it does not reset the DSP hardware. DMA must be
disabled to use the host interrupt.
MOTOROLA
;Enable HI
;Turn off XMT and RCV interrupts
;Turn on host interrupt
;Unmask interrupts
;Wait for HF0 (from host) set
;Enable host receive interrupt
;Now wait for interrupt
DSP56012 User's Manual
Parallel Host Interface
Host Interface (HI)
4-53
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