Data Transfer Optimization Hints - Motorola DSP56600 Manual

Using the DMA

Data Transfer Optimization Hints

4-12 Optimizing DSP56300/DSP56600 Applications
4.5 DATA TRANSFER OPTIMIZATION HINTS
Some points should be bared in mind when optimizing the code for
performance:
• While transferring words between two data memory
locations takes approximately the same number of cycles if
done either by software or by DMA, the DMA has an
advantage when transferring to or from program memory.
This is due to the 6 cycles required for every software access
(MOVEM instruction) to program memory.
• The DSP56300 memory RAM is organized in 256-word
blocks (addresses in a block share the sixteen Most
Significant Bits of the address). A ROM block is 3 K words
long. If both the core and the DMA access addresses in the
same block, the DMA access stalls until the core stops its
access to that block. To avoid such stalls, the core and the
DMA should be made to work on separate memory blocks.
However, in case requirements for overall efficiency
outweigh possible stalls, the programmer should still be
aware of the possible DMA stall, and perhaps write the loops
so that the core will not access the same memory block in
every clock. The following loop generates an access to the
source memory block every clock, and will stall a parallel
DMA transfer to that block for as long as the loop lasts:
move
move
DO
move
move
_BE_NASTY_TO_DMA
move
move
• The following more considerate loop lasts longer, but enables
the DMA to access the memory block, too:
DO
move
move
_IM_OK_DMA_OK
x:(r0)+,a
x:(r0)+,b
#(N/2-1),_BE_NASTY_TO_DMA
x:(r0)+,aa,y:(r4)+
x:(r0)+,bb,y:(r4)+
a,y:(r4)+
b,y:(r4)+
#N,_IM_OK_DMA_OK
x:(r0)+,x0 ;r0 points to memory block
;also used by the DMA
x0,y:(r4)+ ;r4 points to other
;internal memory
;r0 points to the
;memory block that is
;also used by the DMA
;r4 points to other
;internal memory
MOTOROLA