Figure 3-6 Interrupt Priority Register (Addr X:$Ffff); Table 3-4 Interrupt Priorities - Motorola DSP56012 User Manual

Memory, Operating Modes, and Interrupts
Interrupt Priority Register
11 10 9
SAL1 SAL0
23 22 21
Reserved, read as 0, and should be written with 0 for future compatibility

Figure 3-6 Interrupt Priority Register (Addr X:$FFFF)

Priority
Highest
Lowest
Highest
3-16
8 7 6 5
IBL2
20 19 18 17
DTL1 DTL0

Table 3-4 Interrupt Priorities

Level 3 (Nonmaskable)
Hardware RESET
Illegal Instruction
NMI
Stack Error
Trace
SWI
Levels 0, 1, 2 (Maskable)
IRQA
IRQB
SAI Receiver Exception
SAI Transmitter Exception
SAI Left Channel Receiver
SAI Left Channel Transmitter
DSP56012 User's Manual
4 3 2 1
IBL1 IBL0 IAL2 IAL1 IAL0
16 15 14 13
HPL1 HPL0 SHL1 SHL0
Interrupt
0
IRQA Mode
IRQB Mode
Reserved
SAI IPL
12
SHI IPL
Host IPL
DAX IPL
Reserved
AA0292.11
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