Table of Contents
Advertisement
2.1 The POWER5 chip
The POWER5 chip features single and simultaneous multi-threaded execution, providing
higher performance in the single-threaded mode than its POWER4™ predecessor at
equivalent frequencies. The POWER5 processor maintains both binary and architectural
compatibility with existing POWER4 processor-based systems and is designed to ensure that
binaries continue executing properly and application optimizations carry forward to newer
systems. Table 2-1 shows highlights and changes between the POWER4 and the POWER5
processor.
Table 2-1 POWER4 to POWER5 comparison
L1 data cache
L2 cache
L3 cache
Memory bandwidth
Simultaneous
multi-threading
Processor addressing
Dynamic power
management
Size
a. FIFO stands for First In First Out
b. LRU stands for Least Recently Used
POWER5 design provides additional enhancements such as virtualization, reliability,
availability, and serviceability (RAS) features at both chip and system levels.
Key enhancements introduced into the POWER5 processor and system design include:
Simultaneous multi-threading
Dynamic resource balancing to efficiently allocate system resources to each thread
Software-controlled thread prioritization
Dynamic power management to reduce power consumption without affecting performance
Micro-Partitioning technology
Virtual storage, virtual Ethernet
Enhanced scalability, parallelism
Enhanced memory subsystem
Figure 2-2 on page 17 shows the high-level structures of POWER5 processor-based
systems. POWER5 processor supports a 1.9 MB on-chip L2 cache, implemented as three
identical slices with separate controllers for each. Either processor core can independently
access each L2 controller. The L3 cache, with a capacity of 36 MB, operates as a backdoor
with separate buses for reads and writes that operate at half processor speed.
16
IBM eServer OpenPower 710 Technical Overview and Introduction
POWER4 design
2-way set associative FIFO
8-way set associative 1.44 MB
32 MB
118 clock cycles
4 GB/second /chip
No
1 processor
No
412 mm
POWER5 design
a
4-way set associative LRU
10-way set associative 1.9 MB
36 MB
~80 clock cycles
~16 GB/second /chip
Yes
1/10th of processor
Yes
389 mm
b
Advertisement
Table of Contents
