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Architecture and technical
Chapter 2.
overview
This chapter discusses the overall system architecture represented by Figure 2-1. The major
components of this diagram are described in the following sections. The bandwidths provided
throughout this section are theoretical maximums provided for reference. We always
recommend that you obtain real-world performance measurements using production
workloads.
External VHDCI LVD
SCSI connector
P1-T10
2-Port
SCSI
Ultra320
Disk backplane
Figure 2-1 OpenPower 710 server logic data flow
© Copyright IBM Corp. 2005. All rights reserved.
Rack Indicator
SP
SP
Light cable port
Comm. 1
Comm. 2
P1-T5
P1-T6
P1-T7
Service
processor
PCI-X
100 MHz
Control Panel D1
Slim Line Media Device P1-D5
P1-T11-L15-L0
HMC
HMC
RJ45
RJ45
P1-T7
P1-T8
P1-T1
P1-T2
2-Port
10/100/1000
Mbps Ethernet
33 MHz
PCI-X to PCI-X
133 MHz
133 MHz
bridge
66 MHz
PCI-X host
bridge
IDE controller
P1-T12
DIMM C11 J2A "A2"
DIMM C10 J2B "AA"
DIMM C9 J2C "A6"
SMI-II
DIMM C8 J2D "AE"
DIMM C7 J0D "AC"
DIMM C6 J0C "A4"
DIMM C5 J0B "A8"
SMI-II
DIMM C4 J0A "A0"
2
P1-T3
P1-T4
P1-C1
P1-C2
P1-C3
USB
133 MHz
PCI-X to PCI-X
bridge
RIO- 2 hub
RIO-2 Bus
2x1GHz@2B
GX+ Bus
550MHz
ratio 3:1
Processor
module
Core
Core
2x16B
36 MB L3
@825 MHz
Feature
1.9 MB shared L2 cache
POWER5
Memory
controller
Distributed switch
533 MHz
2x8B for read
2x2B for write
15
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