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The simultaneous multi-threading policy is controlled by the operating system and is thus
partition specific.
For Linux, an additional boot option must be set to activate simultaneous multi-threading after
a reboot.
Simultaneous multi-threading features
To improve simultaneous multi-threading performance for various workloads and provide
robust quality of service, the POWER5 processor provides two features:
Dynamic resource balancing
Dynamic resource balancing is designed to ensure that the two threads executing on the
same processor flow smoothly through the system. Depending on the situation, the
POWER5 processor resource balancing logic has different thread throttling mechanisms
(a thread reached threshold of L2 cache misses will be throttled to allow other threads to
pass the stalled thread).
Adjustable thread priority
Adjustable thread priority that allows software to determine when one thread should have
a greater (or lesser) share of execution resources. The POWER5 processor supports eight
software-controlled priority levels for each thread.
Single threading operation
Having threads executing on the same processor will not increase the performance of
applications with execution unit limited performance, or applications that consume all the
chip's memory bandwidth. For this reason, the POWER5 processor supports the single
threading execution mode. In this mode, the POWER5 processor gives all the physical
resources to the active thread, allowing it to achieve higher performance than a POWER4
processor based-system at equivalent frequencies. Highly optimized scientific codes are one
example where a single threading operation may provide more throughput.
2.1.2 Dynamic power management
In current Complementary Metal Oxide Semiconductor (CMOS) technologies, chip power is
one of the most important design parameters. With the introduction of simultaneous
multi-threading, more instructions execute per cycle per processor core, thus increasing the
core's and the chip's total switching power. To reduce switching power, POWER5 chips use a
fine-grained, dynamic clock gating mechanism extensively. This mechanism gates off clocks
to a local clock buffer if dynamic power management logic knows the set of latches driven by
the buffer will not be used in the next cycle. This allows substantial power saving with no
performance impact. In every cycle, the dynamic power management logic determines
whether a local clock buffer that drives a set of latches can be clock gated in the next cycle.
In addition to the switching power, leakage power has become a performance limiter. To
reduce leakage power, the POWER5 chip uses transistors with low threshold voltage only in
critical paths. The POWER5 chip also has a low-power mode, enabled when the system
software instructs the hardware to execute both threads at the lowest available priority. In low
power mode, instructions are dispatched once every 32 cycles at most, further reducing
switching power. The POWER5 chip uses this mode only when there is no ready task to run
on either thread.
18
IBM eServer OpenPower 710 Technical Overview and Introduction
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