Figure 11. Memory Layout; Table 1. I C Addresses For Memory Module Smb - Intel S5000PSLSATAR - Inte Dual LGA771 Specification

®
Intel Server Board S5000PAL / S5000XAL TPS
a total read bandwidth of 21GB/s for four FB-DIMM channels. Thus, this provides 10.7 GB/s of write
memory bandwidth for four FB-DIMM channels. The total bandwidth is based on read bandwidth thus the
total bandwidth is 17 GB/s for 533 and 21.0 GB/s for 667.
On the Intel® Server Board S5000PAL / S5000XAL, a pair of channels becomes a branch where Branch
0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are
organized into two branches for support of RAID 1(mirroring).
To boot the system, the system BIOS on the server board uses a dedicated I
information needed to program the MCH memory registers. The following table provides the I
addresses for each DIMM slot.
3.1.3.1 Memory RASUM Features
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and
Manageability) features. These features include the Intel
SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors,
Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. See the Intel
Server Board Family Datasheet for more information describing these features.
3.1.3.2 Supported Memory
The server board supports up to eight DDR2-533 or DDR2-667 Fully Buffered DIMMs (FBD memory).
The following tables show the maximum memory configurations supported using the specified memory
technology.
Revision 1.9
Branch 0
Branch 1

Figure 11. Memory Layout

2
Table 1. I C Addresses for Memory Module SMB
Device
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Intel order number: D31979-010
Channel B
Channel A
Address
0xA0
0xA2
0xA0
0xA2
0xA0
0xA2
0xA0
0xA2
i
®
x4 Single Device Data Correction (Intel
Functional Architecture
Channel C
Channel D
TP02299
2
C bus to retrieve DIMM
2
C
®
®
S5000 Series Chipsets
x4
27