Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 46

Workaround: Software should not set bit 7 in any PML4E or PDPTE that has Present Bit (Bit
0) set to "1".
For the steppings affected, see the Summary Tables of Changes.
Status:
AW77. Not-Present Page Faults May Set the RSVD Flag in the Error Code
An attempt to access a page that is not marked present causes a page
Problem:
fault. Such a page fault delivers an error code in which both the P flag (bit 0)
and the RSVD flag (bit 3) are 0. Due to this erratum, not-present page faults
may deliver an error code in which the P flag is 0 but the RSVD flag is 1.
Implication: Software may erroneously infer that a page fault was due to a reserved-bit
violation when it was actually due to an attempt to access a not-present
page. Intel has not observed this erratum with any commercially available
software.
Workaround: Page-fault handlers should ignore the RSVD flag in the error code if the P flag
is 0.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW78. VM Exits Due to "NMI-Window Exiting" May Be Delayed by One
Instruction
If VM entry is executed with the "NMI-window exiting" VM-execution control
Problem:
set to 1, a VM exit with exit reason "NMI window" should occur before
execution of any instruction if there is no virtual-NMI blocking, no blocking of
events by MOV SS, and no blocking of events by STI. If VM entry is made
with no virtual-NMI blocking but with blocking of events by either MOV SS or
STI, such a VM exit should occur after execution of one instruction in VMX
non-root operation. Due to this erratum, the VM exit may be delayed by one
additional instruction.
Implication: VMM software using "NMI-window exiting" for NMI virtualization should
generally be unaffected, as the erratum causes at most a one-instruction
delay in the injection of a virtual NMI, which is virtually asynchronous. The
erratum may affect VMMs relying on deterministic delivery of the affected VM
exits.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW79. FP Data Operand Pointer May Be Incorrectly Calculated After an FP
Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit
Address Size in 64-bit Mode
The FP (Floating Point) Data Operand Pointer is the effective address of the
Problem:
operand associated with the last non-control FP instruction executed by the
processor. If an 80-bit FP access (load or store) uses a 32-bit address size in
64-bit mode and the memory access wraps a 4-Gbyte boundary and the FP
46
Errata
® ™
Intel Core 2 Duo Processor
Specification Update