Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 19

Errata
AW3. Store to WT Memory Data May be Seen in Wrong Order by Two
Subsequent Loads
When data of Store to WT memory is used by two subsequent loads of one
Problem:
thread and another thread performs cacheable write to the same address the
first load may get the data from external memory or L2 written by another
core, while the second load will get the data straight from the WT Store.
Implication: Software that uses WB to WT memory aliasing may violate proper store
ordering.
Workaround: Do not use WB to WT aliasing.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW4. Non-Temporal Data Store May be Observed in Wrong Program Order
When non-temporal data is accessed by multiple read operations in one
Problem:
thread while another thread performs a cacheable write operation to the same
address, the data stored may be observed in wrong program order (i.e. later
load operations may read older data).
Implication: Software that uses non-temporal data without proper serialization before
accessing the non-temporal data may observe data in wrong program order.
Workaround: Software that conforms to the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A, section "Buffering of Write Combining
Memory Locations" will operate correctly.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW5. Page Access Bit May be Set Prior to Signaling a Code Segment Limit
Fault
If code segment limit is set close to the end of a code page, then due to this
Problem:
erratum the memory page Access bit (A bit) may be set for the subsequent
page prior to general protection fault on code segment limit.
Implication: When this erratum occurs, a non-accessed page which is present in memory
and follows a page that contains the code segment limit may be tagged as
accessed.
Workaround: Erratum can be avoided by placing a guard page (non-present or non-
executable page) as the last page of the segment or after the page that
includes the code segment limit.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW6. Updating Code Page Directory Attributes without TLB Invalidation May
Result in Improper Handling of Code #PF
Code #PF (Page Fault exception) is normally handled in lower priority order
Problem:
relative to both code #DB (Debug Exception) and code Segment Limit
® ™
Intel Core 2 Duo Processor
Specification Update 19