Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 20

Violation #GP (General Protection Fault). Due to this erratum, code #PF may
be handled incorrectly, if all of the following conditions are met:
• A PDE (Page Directory Entry) is modified without invalidating the
corresponding TLB (Translation Look-aside Buffer) entry
• Code execution transitions to a different code page such that both
• One of the following simultaneous exception conditions is present
following the code transition
Implication: Software may observe either incorrect processing of code #PF before code
Segment Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW7. Storage of PEBS Record Delayed Following Execution of MOV SS or STI
When a performance monitoring counter is configured for PEBS (Precise Event
Problem:
Based Sampling), overflow of the counter results in storage of a PEBS record
in the PEBS buffer. The information in the PEBS record represents the state
of the next instruction to be executed following the counter overflow. Due to
this erratum, if the counter overflow occurs after execution of either MOV SS
or STI, storage of the PEBS record is delayed by one instruction.
Implication: When this erratum occurs, software may observe storage of the PEBS record
being delayed by one instruction following execution of MOV SS or STI. The
state information in the PEBS record will also reflect the one instruction delay.
Workaround: None identified.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW8. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not
Count Some Transitions
Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask
Problem:
01H) counts transitions from x87 Floating Point (FP) to MMX™ instructions.
Due to this erratum, if only a small number of MMX instructions (including
EMMS) are executed immediately after the last FP instruction, a FP to MMX
transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX
may be lower than expected. The degree of undercounting is dependent on
the occurrences of the erratum condition while the counter is active. Intel has
not observed this erratum with any commercially available software.
20
The target linear address corresponds to the modified PDE
o
The PTE (Page Table Entry) for the target linear address has an
o
A (Accessed) bit that is clear
Code #DB and code #PF
o
Code Segment Limit Violation #GP and code #PF
o
Errata
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Intel Core 2 Duo Processor
Specification Update