Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 42

Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW66. When Intel® Deep Power-Down State is Being Used,
IA32_FIXED_CTR2 May Return Incorrect Cycle Counts
When the processor is operating at an N/2 core to front side bus ratio, after
Problem:
exiting an Intel Deep Power-Down State, the internal increment value for
IA32_FIXED_CTR2 (Fixed Function Performance Counter 2, 30BH) will not
take into account the half ratio setting.
Implication: Due to this erratum, IA32_FIXED_CTR2 MSR will not return reliable counts
after returning from an Intel Deep Power-Down State.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW67. Enabling PECI via the PECI_CTL MSR Does Not Enable PECI and May
Corrupt the CPUID Feature Flags
Writing PECI_CTL MSR (Platform Environment Control Interface Control
Problem:
Register) will not update the PECI_CTL MSR (5A0H), instead it will write to
the VMM Feature Flag Mask MSR (CPUID_FEATURE_MASK1, 478H).
Implication: Due to this erratum, PECI (Platform Environment Control Interface) will not
be enabled as expected by the software. In addition, due to this erratum,
processor features reported in ECX following execution of leaf 1 of CPUID
(EAX=1) may be masked. Software utilizing CPUID leaf 1 to verify processor
capabilities may not work as intended.
Workaround: It is possible for the BIOS to contain a workaround for this erratum. Do not
initialize PECI before processor update is loaded. Also, load processor update
as soon as possible after RESET as documented in the RS – Wolfdale
Processor Family Bios Writers Guide, Section 14.8.3 Bootstrap Processor
Initialization Requirements.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW68. INIT Incorrectly Resets IA32_LSTAR MSR
In response to an INIT reset initiated either via the INIT# pin or an IPI (Inter
Problem:
Processor Interrupt), the processor should leave MSR values unchanged. Due
to this erratum IA32_LSTAR MSR (C0000082H), which is used by the iA32e
SYSCALL instruction, is being cleared by an INIT reset.
Implication: If software programs a value in IA32_LSTAR to be used by the SYSCALL
instruction and the processor subsequently receives an INIT reset, the
SYSCALL instructions will not behave as intended. Intel has not observed this
erratum in any commercially available software.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
42
Errata
® ™
Intel Core 2 Duo Processor
Specification Update