Intel CORE 2 DUO E7000 - SPECIFICATION UPDATE 7-2010 Specification page 28

Implication: Software may encounter unexpected page fault or incorrect address
translation due to a TLB entry erroneously left in TLB after INIT.
Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or
PE) registers before writing to memory early in BIOS code to clear all the
global entries from TLB.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW29. Split Locked Stores May not Trigger the Monitoring Hardware
Logical processors normally resume program execution following the MWAIT,
Problem:
when another logical processor performs a write access to a WB cacheable
address within the address range used to perform the MONITOR operation.
Due to this erratum, a logical processor may not resume execution until the
next targeted interrupt event or O/S timer tick following a locked store that
spans across cache lines within the monitored address range.
Implication: The logical processor that executed the MWAIT instruction may not resume
execution until the next targeted interrupt event or O/S timer tick in the case
where the monitored address is written by a locked store which is split across
cache lines.
Workaround: Do not use locked stores that span cache lines in the monitored address
range.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW30. Programming the Digital Thermal Sensor (DTS) Threshold May Cause
Unexpected Thermal Interrupts
Software can enable DTS thermal interrupts by programming the thermal
Problem:
threshold and setting the respective thermal interrupt enable bit. When
programming DTS value, the previous DTS threshold may be crossed. This
will generate an unexpected thermal interrupt.
Implication: Software may observe an unexpected thermal interrupt occur after
reprogramming the thermal threshold.
Workaround: In the ACPI/OS implement a workaround by temporarily disabling the DTS
threshold interrupt before updating the DTS threshold value.
For the steppings affected, see the Summary Tables of Changes.
Status:
AW31. Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Software which is written so that multiple agents can modify the same shared
Problem:
unaligned memory location at the same time may experience a memory
ordering issue if multiple loads access this shared data shortly thereafter.
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• TLB entry is present in TLB when INIT occurs
Errata
® ™
Intel Core 2 Duo Processor
Specification Update