Sharp ER-A450T Service Manual page 29

Receipt feed motor: The motor rotates counterclockwise.
Step No.
A
1 ON OFF
2 ON OFF
3 OFF
4 OFF
Journal feed motor: The motor rotates clockwise.
Step No.
A
1 ON OFF
2 ON OFF
3 OFF
4 OFF
Note 1: ON = Conducting
OFF = Not conducting
Note 2: The step No. is performed by the internal process of TPRC1.
When the motor is locked, the circuit is connected to the CPU
through MPCA6.
3) Print circuit
STRB1~STRB5
LATCH
Thermal
printer
SO
TPRC 1
PB head
SI
RAM
CLOCK
VHCOM
VRES
8. Drawer drive circuit
VRESC
51 DR0
IC9
52 DR1
CPU
TD62308F
50
DOSP
R163
C105
47K
1000P
Fig. 8-1
The drawer is directly supported by the CPU. No action starts when
the power supply is not steady as the output stage of the driver is
pulled VP by VRESC signal.
Drawer open and close is sensed with the microswitch provided in the
drawer whose signal level is converted with R161 and R162 which is
read directly by the CPU.
Phase
B C D
ON OFF
OFF ON
ON OFF ON
ON ON OFF
Phase
B C D
OFF ON
ON OFF
ON ON OFF
ON OFF ON
VH
+24V
+24V +24V
DRAW0
Drawer
DRAW1
solenoid
R161 22K
R162
4.7K
9. Key, display, time buzzer controls
MPCA7
HTS1
STH1
SCK1
RESET
INT2
POFF
CPU
P11
P10
P12
RES
P-OFF
RES0
ST0~ST7
KR0~KR7
KR10,KR11
Key board
G1~G10
a~g,DP
Display
B
VCC
BUZZER
1) Power on sequence
During service interruption, the CKDC8 senses POF within 500msec.
When service interruption is cancelled by turning on the power, the
CKDC8 cancels resetting of the CPU in the command mode. After
initializing each port, the CPU reads the start condition (1 byte).
POF
RES1
SHEN
LDRQ
1 2 Start condition
After sampling POF High, the CKDC8 performs a mode scan and key
scan at , then cancels resetting of the CPU. After being cancelled,
the CPU initializes each port at
After being cancelled, the CPU reads the start condition while it also
sets the shift mode. If, however, the first starting is made in other than
SRV mode after the CKDC8 resets the CPU without request from the
CPU, the CKDC8 sets the start condition as if the start condition was
made in SRV mode.
4 – 21
HTS
HTS
STH
STH
SCK
SCK
RESET
RES1
LDRQ
LDRQ
ERC
ECR
SHEN
SHEN
POFF
VDD
RES0
RESET
ST0~ST7
KR0~7,KR10,KR11
Driver
T0~T9
a~g,DP
Driver
2
CKDC 8
Fig. 9-1
Next command
Fig. 9-2
and reads the start condition.