Sharp ER-A450T Service Manual page 26

RAM area memory map
100000H
NOT USE
1C0000H
RAS1 128K Byte
1E0000H
RAS2 128K Byte
200000H
RAS3
512K Byte
(OPTION)
280000H
(MAX 2MB)
400000H
NOT USE
BFFFFFH
Fig. 5-4
Note: RAS2 signal is formed as OR in the image area of 0 page.
(lower32KB).
I/O area memory map
00FF80H
MPCCS
00FFA0H
NOT USE
MCR1 (NOT USE)
MCR2 (NOT USE)
00FFC0H
OPCCS1
00FFD0H
OPCCS2
00FFE0H
NOT USE
00FFE8H
NOT USE
00FFF0H
NOT USE
00FFFFH
Fig. 5-5
Note 1: MPCCS signal is the base signal for MPCA7 internal reg-
ister decoding, and does not exist as an internal signal.
Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC
(optionperipheral controller) using the base signal OPTCS
for option decoding. They does not exist as external sig-
nals.
(*1)
(*2)
(*2)
4 – 18
2) Block diagram
Data bus
ROS1
CPU MPCA6
Address bus
RAS2
Fig. 5-6
ROM control
C80000H~CFFFFFH
C00000H~C7FFFFH
Address
Address
A23~A14
decorder
000000H~007FFFH
(IPLON)
MPCA7
Fig. 5-7
IPLON: IPL board detection signal incorporated in the option slot.
Note used in the ER-A445P. (Not used)
Access is performed with two ROM chip select signals ROS1 and
ROS2, which decode 512KB address area respectively to access-
max. 4MB ROM.
RAM control
200000H~3FFFFFH
1C0000H~1DFFFFH
Address
A23~A14
Address
decorder
008000H~
00F7FFH
*1
DOI D Q
Control register
S8F
CK
R
RESET
Fig. 5-8
Access is performed with two RAM chip select signals, RAS2 and
RAS3. The control register in MPCA7 allows selection of page image
memory area. (RAS1 is selected for initializing.)
: For 0 page image area, selection between RAS2 and RAS3 can
bemade with the control register. The 0 page control register
performs initializing at the timing of no stack process immedi-
ately after resetting.
ROM1
RAM2
RAM1
(OPTION)
RAS3
ROS2
ROS1
RAS3
RAS1
RAS2
1E0000H~1FFFFFH
MPCA7