Sharp ER-A450T Service Manual page 24

Pin
Name ER-A770
NO.
142 VCC VCC
143 GND GND
144 /CSD VCC
145 TRNDTD NC
146 /DTRD NC
147 /RTSD NC
148 RCVDTD GND
149 /CTSD GND
150 /DSRD GND
151 TRNRDYD NC
152 RCVRDYD NC
153 TRNEMPD NC
154 SYCBKD NC
155 /WIN /WRH
156 /RIN /RDH
157 RSLCT0 AH0
158 RSLCT1 AH1
159 RST RES USART
160 MCLK CLK USART
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
3. Clock generator
1) CPU (HD64151010FX)
99
XTAL
CPU
(HD64151010FX)
98
EXTAL
101
Fig. 3-1
Basic clock is supplied from a 19.66 MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
I/O Description
+5V
GND
IS +5V
O NC
O NC
O NC
IS GND
IS GND
IS GND
O NC
O NC
O NC
IO NC
I Write signal
I Read signal
I Address bus
I Address bus
IS Reset signal
I Clock (4.91MHz)
X4
19.66MHz
PHAI
4 – 16
2) CKDC8 oscillation circuit
40
X2
41
X1
CKDC 8
37
XT2
38
XT1
C106
18P
HD404728A91FS
Fig. 3-2
Two oscillators are connected to the CKDC8.
The main clock X1 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
R114
8.2KG
R115
15KG
+
MPCA7
C83
1µ 50V
R116
9.1KG
13 54 48
POFF
89
IRQ0 1
RESET (FROM CKDC 8)
CPU
72
STOP (TO CKDC 8)
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal STOP forced low to prepare for the power-off situation.
The signal STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
This circuit monitors +24V supply voltage.
X1
4.19MHz
1
2
3
R164
330K
X2
32.768KHz
C105
33P
+24V +5V
D7
1SS133
R117 R119
2.7K 2.7K
R118
56K
8
3 B
+
1
/POFF
2
-
IC7A
4
KIA393F
ZD2
C37
MTZ5.1A
1000P