Sharp ER-A450T Service Manual page 27

6. SSP circuit
1) Block diagram
This is the circuit employed for implementing the Special Service
Preset(SSP).
(Block diagram)
NMI
A0~23
D0~D7
CPU
Fig. 6-1
(MPCA7 block diagram)
BAR 0
D0~
D7
BAR N
REGCS
Decode
A23~
A0
Control signal
ROMCS
Fig. 6-2
A19 A18 A17 A16 A15
1
Upper bits
Don't care for "-----."
SSPRQ
MPCA7
Comparator
Coincide
O
SSPRQ
(NMI)
N
Coincide
SPE
(Enable register)
2
Intermediate bits
< BAR composition >
As the address detection system, the break address register compari-
son system is employed though the mapping system and employed in
the conventional monitor RAM. The address register located in MPCA
is always compared with the system address bus to monitor and
generate the NMI signal at a synchronized timing and to go to the
NMI exception process.
In the exception process routine of the service routine, the entry
address is checked to go to the SSP sub routine.
Entry to the break address register (BAR) is performed through the
address FFFF00H or later decoded in MPCA7.
2) SSP register
The break address register (BAR) is accessed through the direct
address of FFFF00H~FFFFFFH. Entry number is 32 entry.
7
FFFF00
H
1
2
3
4
5
6
7
Each BAR is composed of 4 a byte address. The bit composition is as
follows:
A8 A7 A2
3
Lower bits
Fig. 6-4
is the enable register. The entry registers of the break address are
assigned to , , and
bit position, writing to ,
corresponding area is the 1MB space of ROS1 and ROS2.
4 – 19
0
1
2
BAR0
3
4
BAR1
BAR2
Fig. 6-3
EN
4
Enable register
EN (bit7) = 1 Enable
= 0 Inhibit
. Each bit of address corresponds to each
, and is performed without shifting. The