Sampling Times And Processing Sequence - Siemens SIMOVERT FC Series Operating Instructions Manual

Function Descriptions
H333 on block diagram sheet 30 applies fixed value 1 or 1000 to the multiplier element for the D
component of the technology controller.
Display parameters
The values of certain signals can be displayed in display parameters (d parameters). It is possible to link all
connectors to display parameters using connector displays (block diagram sheet 8) and thus to display their
values.
Representation in block diagram:
d010
Display parameter
Parameter number = d010
3.2

Sampling times and processing sequence

One characteristic of the T100 technology board as a microprocessor-based controller module is that the
individual function blocks are processed sequentially and cyclically at specific time intervals (computing cycle ).
Consequently, the reaction of a function block to a change in an input quantity will be delayed by up to one
computing cycle.
The function blocks of the T100 technology board are processed on 2 time levels with different cycle times:
• Background tasks (background programs) with a computing cycle of 20 ms (i.e. every function block is
processed once every 20 ms):
Representation in block diagram
B10
= Background task 10
Processing sequence according to task number (B10 before B20 and so on)
• Foreground tasks (foreground programs) with a computing cycle of 2.2 ms (e.g. every function block is
processed once every 2.2 ms):
Representation in block diagram
F10
= Foreground task 10
Processing sequence according to task number (F10 before F20 and so on)
Since it is possible to configure the available function blocks freely, very long, undesirable signal delays may
result if the time sequence in which the blocks are processed (task numbers) is not observed.
For this reason, functions which can be programmed multiply (e.g. 5 adders, 16 AND gates, etc.) are not
positioned in the processing sequence so as to be processed chronologically, but are distributed over the
computing cycle in such a way (e.g. AND gate 1 = F500 to AND gate 16 = F1570 - see block diagram sheet 32)
that it is possible in most cases to include all the desired functions in the processing sequence without incurring
long runtimes.
The processing sequence of foreground tasks F200 to F1650 can be altered in parameters H750 to H752 (see
also Chapter 4 / parameters H750 to H752).
Starting with software version 1.1 the optimum processing sequence can be implemented by setting H750 = 2.
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T100 Technology Board Manual for Software Module MS100 "Multi-Purpose Drive"
Siemens AG 6SE7087-6CX84-0BB1
02.99