Timing Specifications - National Instruments PXI-6070E User Manual

Chapter 4 Digital I/O

Timing Specifications

E Series User Manual
voltage across the pull-down resistor above a TTL-low level of 0.4 VDC.
Figure 4-2 shows the DIO configuration for high DIO power-on state.
Device
82C55
Figure 4-2. DIO Configuration for High DIO Power-On State
The following steps show how to calculate the value of R
achieve a TTL-low power-on state for a single DIO line.
Using the following formula, calculate the largest possible load to maintain
a logic low level of 0.4 V and supply the maximum driving current:
where:
I = 46 µA (4.6 V across the 100 kΩ pull-up resistor) + 10 µA (10 µA
maximum leakage current)
Therefore:
This resistor value, 7.1 kΩ, provides a maximum of 0.4 V on the DIO line
at power-on. You can substitute smaller resistor values to lower the voltage
or to provide a margin for V
(NI 6016 and NI 6025E Devices Only)
specifications for handshaking with the P3.<0..7> lines. The handshaking
lines STB* and IBF synchronize input transfers. The handshaking lines
OBF* and ACK* synchronize output transfers. Table 4-2 describes signals
appearing in the handshaking diagrams.
+5 V
100 k
R
GND
V = I × R → R = V/I
L L
V = 0.4 V Voltage across R
R = 7.1 kΩ (0.4 V/56 µA)
L
variations and other factors.
cc
This section lists the timing
4-4
Digital I/O Line
L
needed to
L
L
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