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Chapter 4
Connecting Signals
Timing Specifications for Digital I/O Ports A, B, and C
Programming
Mode
Mode 0
Mode 1 Input
Mode 1 Output
AT E Series User Manual
If an internal timebase clock is used, the gate signal cannot be synchronized
with the clock. In this case, gates applied close to a source edge take effect
either on that source edge or on the next one. This arrangement results in
an uncertainty of one source clock period with respect to unsynchronized
gating sources.
The OUT output timing parameters are referenced to the signal at the
SOURCE input or to one of the internally generated clock signals on
the AT E Series devices. Figure 4-37 shows the OUT signal referenced to
the rising edge of a source signal. Any OUT signal state changes occur
within 80 ns after the rising or falling edge of the source signal.
FREQ_OUT Signal
This signal is available only as an output on the FREQ_OUT pin. The
FREQ_OUT signal is the output of the AT E Series device frequency
generator. The frequency generator is a 4-bit counter that can divide its
input clock by the numbers 1 through 16. The input clock of the frequency
generator is software selectable from the internal 10 MHz and 100 kHz
timebases. The output polarity is software selectable. This output is set to
high-impedance at startup.
AT-MIO-16DE-10 only
In addition to its function as a digital I/O port, digital port C, PC<0..7>, can
also be used for handshaking when performing data transfers with ports A
and B. The signals assigned to port C depend on the mode in which it is
programmed. In mode 0, port C is considered two 4-bit I/O ports. In modes
1 and 2, port C is used for status and handshaking signals with two or three
additional I/O bits. Table 4-7 summarizes the signal assignments of port C
for each programmable mode. Refer to Table 4-7 for descriptions of the
signals for port C.
Table 4-7. Port C Signal Assignments
Group A
PC7
PC6
I/O
I/O
I/O
I/O
I/O
IBF
OBF
*
ACK
*
I/O
A
A
PC5
PC4
PC3
I/O
I/O
STB
*
INTR
A
A
I/O
INTR
4-50
Group B
PC2
PC1
I/O
I/O
STB
*
IBFB
A
B
B
ACK
*
OBF
*
A
B
B
PC0
I/O
INTR
B
INTR
B
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