Timing Specifications - National Instruments PC-DIO-96/PnP User Manual

Chapter 3 Signal Connections

Timing Specifications

PC-DIO-96/PnP User Manual
Example:
At power up, the board is configured for input and jumper W1 is set in
the low DIO power-up state, which means all DIO lines are pulled low.
If you want to pull one channel high, follow these steps:
1. Install a load (R
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greater the current consumption and the lower the voltage (V).
2. Using the following formula, calculate the largest possible load to
maintain a logic high level of 2.8 V and supply the maximum sink
current (I).
⇒ R
V = I * R
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V = 2.2 V
I = 28 µA + 10 µA
Therefore:
RL = 5.7 kΩ
This resistor value, 5.7 kΩ, provides a minimum of 2.8 V on the DIO
line at power up. You can substitute smaller resistor values but they will
draw more current, leaving less sink current for other circuitry
connected to this line. The 5.7 kΩ resistor will reduce the amount of a
logic low sink current by 0.8 mA with a 0.4 V output.
This section lists the timing specifications for handshaking with the
PC-DIO-96/PnP. The handshaking lines STB* and IBF synchronize
input transfers. The handshaking lines OBF* and ACK* synchronize
output transfers.
The signals in Table 3-2 are used in the timing diagrams later in this
chapter.
). Remember that the smaller the resistance, the
= V / I, where:
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; voltage across R
; 2.8 V across the 100 kΩ pull-up
resistor and 10 µA from 82C55
leakage current
; 2.2 V / 38 µA
3-12
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