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National Instruments DIO 6533 manual available for free PDF download: User Manual
National Instruments DIO 6533 User Manual (125 pages)
High-Speed Digital I/O Boards for PCI, PXI, CompactPCI, AT, EISA, or PCMCIA Bus Systems
Brand:
National Instruments
| Category:
I/O Systems
| Size: 0.76 MB
Table of Contents
User Manual
1
Important Information
3
Table of Contents
4
About this Manual
9
Organization of this Manual
9
Conventions Used in this Manual
10
National Instruments Documentation
10
Related Documentation
11
Customer Communication
12
Appendix A Figure
13
Using PXI with Compactpci
14
Table 1-1. Pins Used by the PXI-6533 Device
15
What You Need to Get Started
15
Software Programming Choices
16
National Instruments Application Software
16
NI-DAQ Driver Software
17
Register-Level Programming
18
Figure 1-1. the Relationship between the Programming Environment, NI-DAQ, and Your Hardware
18
Optional Equipment
19
Unpacking
20
Chapter 1 Introduction
13
About the DIO 6533 Devices
13
Chapter 2 Installation and Configuration
21
Software Installation
21
Hardware Installation
21
Installing the PCI-DIO-32HS
21
Figure
21
Installing the PXI-6533
22
Installing the AT-DIO-32HS
23
Installing the Daqcard-6533
23
PCI, PXI, and Daqcard Device Configuration
24
Figure 2-1. Daqcard-6533 Completed Installation
24
AT Device Configuration
25
Bus Interface
25
Plug and Play Mode
25
Switchless Data Acquisition
25
Base I/O Address Selection
26
DMA Channel Selection
26
Interrupt Channel Selection
26
Table 2-1. PC at I/O Address Map
26
Table 2-2. PC at Interrupt Assignment Map
28
Table 2-3. PC at 16-Bit DMA Channel Assignment Map
29
Chapter 3 Hardware Overview
30
Figure
30
Figure 3-1. PCI-DIO-32HS/PXI-6533 Block Diagram
31
Figure 3-2. AT-DIO-32HS Block Diagram
32
Figure 3-3. Daqcard-6533 Block Diagram
33
Unstrobed I/O
33
Strobed I/O-Pattern Generation and Handshaking
34
Pattern and Change Detection
35
Pattern-Detection Triggers
35
Change Detection
36
Figure 3-4. Pattern Detection Example
36
Handshaking Protocols
37
Message Generation
37
8255 Emulation
38
Leading-Edge Pulse
38
Level ACK
38
Long Pulse
38
Trailing-Edge Pulse
38
Burst Mode
39
Comparing Protocols
39
Table 3-1. 6533 Handshaking Protocols
40
Controlling the Startup Sequence
41
Starting a Handshaking Transfer
41
Controlling Line Polarities
42
Transfer Rates
42
Chapter 4 Signal Connections
44
I/O Connector
44
Figure
44
Figure 4-1. 6533 Device I/O Connector Pin Assignments
45
Signal Descriptions
46
Table 4-1. Signal Descriptions
46
Signal Characteristics
49
Control Signal Summary
50
RTSI Bus Interface
50
Board and RTSI Clocks
51
RTSI Triggers
51
Data Signal Connections
52
Figure 4-2. RTSI Bus Signal Connection
52
Unstrobed I/O
53
Figure 4-3. Example of Data Signal Connections
54
Strobed I/O
55
Timing Connections
56
Pull-Up and Pull-Down Connections
56
Power Connections
57
Field Wiring and Termination
57
Figure 4-4. Transmission Line Terminations
59
Chapter 5 Signal Timing
60
Pattern-Generation Timing
60
Figure 5-1. Pattern-Generation Timing
60
Request Timing
61
External Requests
61
Figure 5-2. Internal Request Timing
61
Internal Requests
61
Figure 5-3. External Request Timing
62
Trigger Timing
62
Handshake Timing
63
8255 Emulation
63
Figure 5-4. Trigger Input Signal Timing
63
Input
64
Figure 5-5. 8255 Emulation Mode Input
65
Output
65
Figure 5-6. 8255 Emulation Mode Output
66
8255 Emulation Mode Timing Specifications
67
Figure 5-7. 8255 Emulation Timing
67
Other Asynchronous Modes
68
Input
68
Level-ACK Mode
68
Figure 5-8. Level-ACK Mode Input
69
Output
69
Figure 5-9. Level-ACK Mode Output
70
Level-ACK Mode Timing Specifications
70
Figure 5-10. Level-ACK Mode Input Timing
71
Figure 5-11. Level-ACK Mode Output Timing
72
Input
73
Leading-Edge Mode
73
Output
73
Figure 5-12. Leading-Edge Mode Input
74
Figure 5-13. Leading-Edge Mode Output
75
Leading-Edge Mode Timing Specifications
75
Figure 5-14. Leading-Edge Mode Input Timing
76
Figure 5-15. Leading-Edge Mode Output Timing
77
Figure 5-16. Long-Pulse Mode Input
78
Long-Pulse Mode
78
Figure 5-17. Long-Pulse Mode Output
79
Long-Pulse Mode Timing Specifications
79
Figure 5-18. Long-Pulse Mode Input Timing
80
Figure 5-19. Long-Pulse Mode Output Timing
81
Input
82
Output
82
Trailing-Edge Mode
82
Figure 5-20. Trailing-Edge Mode Input
83
Figure 5-21. Trailing-Edge Mode Output
84
Trailing-Edge Mode Timing Specifications
84
Figure 5-22. Trailing-Edge Mode Input Timing
85
Burst Mode
86
Figure 5-23. Trailing-Edge Mode Output Timing
86
Burst Mode Timing Specifications
87
Figure 5-24. Input Burst Mode Transfer Example
87
Figure 5-25. Output Burst Mode Transfer Example
88
Figure 5-26. Burst Mode Output Timing (Default)
89
Figure 5-27. Burst Mode Input Timing (Default)
90
Figure 5-28. Burst Mode Output Timing (PCLK Reversed)
91
Figure 5-29. Burst Mode Input Timing (PCLK Reversed)
92
Pattern Generation
95
Power Requirement
100
Figure B-1. 68-To-50-Pin Adapter Pin Assignments
103
Electronic Services
104
Telephone and Fax Support
105
Configuration Form
107
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