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Chapter 5
Counters
Counter 0 Up/Down Signal
Counter 1 Source Signal
E Series User Manual
CTR 0 OUT Pin
When the CTR 0 OUT pin is configured as an output, the
Ctr0InternalOutput signal drives the pin. As an input, CTR 0 OUT can
drive any of the RTSI <0..6> signals. CTR 0 OUT is set to high-impedance
at startup. Figure 5-6 shows the relationship of CTR 0 OUT and
Ctr0InternalOutput.
Ctr0Gate
Counter 0
Ctr0Source
Ctr0Up/Down
Figure 5-6. CTR 0 OUT and Ctr0InternalOutput
You can externally input this signal on the P0.6 pin, but it is not available
as an output on the I/O connector. When you enable externally controlled
count direction, Counter 0 counts down when this pin is at a logic low and
counts up when it is at a logic high. If you are using an external signal to
control the count direction, do not use the P0.6 pin for output. If you do not
enable externally controlled count direction, the P0.6 pin is free for general
use.
You can select any PFI as well as many other internal signals as the Counter
1 Source (Ctr1Source) signal. The Ctr1Source signal is configured in
edge-detection mode on either rising or falling edge. The selected edge of
the Ctr1Source signal increments and decrements the counter value
depending on the application the counter is performing.
You can export the Counter 1 signal to the PFI 3/CTR 1 SOURCE pin, even
if another PFI is inputting the Ctr1Source signal. This output is set to
high-impedance at startup.
Can Drive RTSI <0..6>,
ai/SampleClock,
ai/StartTrigger,
or other signals
Ctr0InternalOutput
Ctr0Out
Can Drive RTSI <0..6>
5-6
CTR 0 OUT
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