Intel Core 2 Duo User Manual page 13

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Abou t Th is M a n u a l—I n t e l
Ta ble 1 . Acr on ym s ( She e t 3 of 3 )
Acr on ym
MHz
OEM
PCI e
PCM
POST
PLC
RAI D
RTC
SATA
SI O
SMBus
SODI MM
SPD
SPI
SSO
STR
TCO
TCP
TDM
TDR
µBGA
UDP
UHCI
USB
VGA
VI D
VREG
XDP
May 2007
Order Num ber: 317443- 001US
9 4 5 GM E Ex pr e ss Ch ipse t
Mega- Hert z
Original Equipm ent Manufact urer
PCI Express*
Pulse Code Modulat ion
Power On Self Test
Plat form LAN Connect
Redundant Array of I nexpensive Disks
Real Tim e Clock
Serial ATA
Super I nput / Out put
Syst em Managem ent Bus
Sm all Out line Dual I n- line Mem ory Module
Serial Presence Det ect
Serial Peripheral I nt erface
Sim ult aneous Swit ching Out put
Suspend To RAM
Tot al Cost of Ow nership
Transm ission Cont rol Prot ocol
Tim e Division Mult iplexed
Tim e Dom ain Reflect om et ry
Micro Ball Grid Array
User Dat agram Prot ocol
Universal Host Cont roller I nt erface
Universal Serial Bus
Video Graphics Adapt er
Volt age I dent ificat ion
Volt age Regulat or
eXt ended Debug Port
®
I nt el Core
D e fin it ion
TM
2 Duo processor wit h t he Mobile I nt el
®
945GME Express Chipset
Manual
13