Glossary Of Term S And Acronym S - Intel Core 2 Duo User Manual

®
Abou t Th is M a n u a l—I n t e l
1 .3 Glossa r y of Te r m s a n d Acr on ym s
This sect ion defines convent ions and t erm inology used t hroughout t his docum ent .
Aggr e ssor
Ant i- e t ch
Assist e d Gun n in g Tr a n sce ive r Logic+
Asyn chr on ou s GTL+ The processor does not ut ilize CMOS volt age levels on any
Bus Age nt
Cr osst a lk
Flight Tim e
May 2007
Order Num ber: 317443- 001US
9 4 5 GM E Ex pr e ss Ch ipse t
A net work t hat t ransm it s a coupled signal t o anot her net work.
Any plane- split , void or cut out in a VCC or GND plane.
The front- side bus uses a bus t echnology called AGTL+ , or
Assist ed Gunning Transceiver Logic. AGTL+ buffers are open-
drain, and require pull- up resist ors t o provide t he high logic level
and t erm inat ion. AGTL+ out put buffers differ from GTL+ buffers
wit h t he addit ion of an act ive pMOS pull- up t ransist or t o assist
t he pull- up resist ors during t he first clock of a low- t o- high
volt age t ransit ion.
signals t hat connect t o t he processor. As a result , legacy input
signals such as A20M# , I GNNE# , I NI T# , LI NT0/ I NTR, LI NT1/
NMI , PWRGOOD, SMI # , SLP# , and STPCLK# ut ilize GTL+ input
buffers. Legacy out put signals ( FERR# and I ERR# ) and non-
AGTL+ signals ( THERMTRI P# and PROCHOT# ) also ut ilize GTL+
out put buffers. All of t hese signals follow t he sam e DC
requirem ent s as AGTL+ signals, however t he out put s are not
act ively driven high ( during a logical 0 t o 1 t ransit ion) by t he
processor ( t he m aj or difference bet ween GTL+ and AGTL+ ) .
These signals do not have set up or hold t im e specificat ions in
relat ion t o BCLK[ 1: 0] , and are t herefore referred t o as
"Asynchronous GTL+ Signals". However, all of t he Asynchronous
GTL+ signals are required t o be assert ed for at least t wo BCLKs
in order for t he processor t o recognize t hem .
A com ponent or group of com ponent s t hat , when com bined,
represent a single load on t he AGTL+ bus.
The recept ion on a vict im net work of a signal im posed by
aggressor net work( s) t hrough induct ive and capacit ive coupling
bet ween t he net works.
• Backward Crosst alk - Coupling t hat creat es a signal in a
vict im net work t hat t ravels in t he opposit e direct ion as t he
aggressor 's signal.
• Forward Crosst alk - Coupling t hat creat es a signal in a
vict im net work t hat t ravels in t he sam e direct ion as t he
aggressor 's signal.
• Even Mode Crosst alk - Coupling from a signal or m ult iple
aggressors when all t he aggressors swit ch in t he sam e
direct ion t hat t he vict im is swit ching.
• Odd Mode Crosst alk - Coupling from a signal or m ult iple
aggressors when all t he aggressors swit ch in t he opposit e
direct ion t hat t he vict im is swit ching.
Flight t im e is a t erm in t he t im ing equat ion t hat includes t he
signal propagat ion delay, any effect s t he syst em has on t he TCO
of t he driver, plus any adj ust m ent s t o t he signal at t he receiver
®
I nt el Core
TM
2 Duo processor wit h t he Mobile I nt el
®
945GME Express Chipset
Manual
9