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Processor 3/6
5
1.05_VCCST
NEAR CPU
Max Length
: < 3" (Near CPU)
space
: 15 mils
R39
Alert# between the CLK & Data
100_04
SVID need avoid the noise
D
47
H_CPU_SVIDDAT
47
H_CPU_SVIDALRT#
47
H_CPU_SVIDCLK
H_PROCHOT#
47
H_PROCHOT#
45
DDR_VTT_PG_CTRL
CLOSE TO CPU
< 0.5"
R299
20_1%_04
26
H_PM_DOWN
TO PCH-H
26
PCH_PECI
R297
*0402_short-p
40
H_PECI
TO EC
C
26
PCH_THERMTRIP#
VCCST_PWRGD
B
R26
20K_04
22,25,40,47
ALL_SYS_PWRGD
C137
*0.1u_10V_X7R_04
G
40
H_PROCHOT_EC
A
R335
100K_04
5
4
3
U30E
R40
B31
29
PCH_CPU_BCLK_R_DP
BCLKP
A32
56.2_1%_04
29
PCH_CPU_BCLK_R_DN
BCLKN
D35
29
PCH_CPU_PCIBCLK_R_DP
PCI_BCLKP
C36
29
PCH_CPU_PCIBCLK_R_DN
PCI_BCLKN
E31
29
CPU_24MHZ_R_DP
CLK24P
D31
29
CPU_24MHZ_R_DN
CLK24N
R41
220_04
BH31
VIDALERT#
VIDALERT#
BH32
VIDSCK
BH29
VIDSOUT
R319
499_1%_04
PROCHOT#
BR30
PROCHOT#
BT13
DDR_VTT_CNTL
CLOSE TO CPU
(0.3" ~ 1.5")
VCCST_PWRGD
VCCST_PWRGD_CPU
R25
60.4_1%_04
H13
VCCST_PWRGD
BT31
27
H_PWRGD
PROCPWRGD
BP35
26
PLTRST_CPU_N
RESET#
PROC_TDO
BM34
26
H_PM_SYNC
PM_DOWN
PM_SYNC
PROC_TDI
BP31
PM_DOWN
PROC_TMS
BT34
PECI
PROC_TCK
J31
THERMTRIP#
H_SKTOCC_N
PROC_TRST#
BR33
28
H_SKTOCC_N
PROC_SELECT#
SKTOCC#
PROC_PREQ#
BN1
PROC_SELECT#
PROC_PRDY#
R382
*0_04
BM30
CATERR#
CFG_RCOMP
AT13
SKL_CNL_N:
ZVM#
FLOAT FOR SKL
AW13
MSM#
GND FOR CNL
AU13
RSVD1
AY13
RSVD2
5 OF 13
CFL_H_62_INT_IP_CRB_CFLH
1.05_VCCST
CLOSE TO CPU
VDD3
(0.3" ~ 1.5")
R42
1K_04
VCCST_PWRGD
R24
100K_04
D
SYS_PWRGD#
2
G
C194
S
Q2A
*0.1u_10V_X7R_04
D
MTDK3S6R
5
G
S
Q2B
MTDK3S6R
1.05DX_VCCSTG
H_PROCHOT#
R322
1K_04
Q32
C550
2SK3018S3
47P_50V_NPO_04
CAD Note: Capacitor need to be placed
close to buffer output pin
4
3
2
CFG[0]: Stall
PLL lock until de-asserted:
—
1 = (Default) Normal Operation;
No stall.
—
0 = Stall.
BN25
CFG0
T11
CFG[1]:
CFG_0
BN27
CFG_1
CFG[2]: PCI Express*
BN26
CFG_2
BN28
Numbering
Reversal.
CFG3
T74
CFG_3
BR20
CFG4
R332
1K_04
—
1 = Normal operation
CFG_4
BM20
CFG5
R58
1K_04
—
0 = Lane numbers reversed.
CFG_5
BT20
CFG6
R341
1K_04
CFG[3]:
CFG_6
BP20
CFG7
CFG[4]:
T84
CFG_7
BR23
CFG8
T82
—
1 = Disabled.
CFG_8
BR22
—
0 = Enabled.
CFG_9
BT23
CFG[6:5]:
CFG_10
BT22
CFG_11
—
00 = 1 x8, 2 x4 PCI Express*
BM19
CFG_12
—
01 = reserved
BR19
CFG_13
—
10 = 2 x8 PCI Express*
BP19
CFG_14
BT19
—
11 = 1 x16 PCI Express*
CFG_15
CFG[7]:
BN23
—
1 = (default) PEG Train
CFG_17
BP23
immediately following RESET# de
CFG_16
BP22
assertion.
CFG_19
BN22
—
0 = PEG Wait for BIOS for
CFG_18
training.
CFG[19:8]:
BR27
BPM#_0
lanes.
BT27
BPM#_1
BM31
BPM#_2
BT30
BPM#_3
PDG P.569
H_TDO
BT28
R333
*0402_short-p
H_TDI
PCH_JTAG_TDO
27
H_TDO
BL32
R21
*0402_short-p
H_TMS
PCH_JTAG_TDI
27
BP28
R38
*0402_short-p
H_TCK
PCH_JTAG_TMS
27
H_TCK
BR28
R334
*0402_short-p
PCH_JTAGX
27
H_TRST#
BP30
R318
*0402_short-p
H_PREQ#
H_TRST#_R
32
BL30
R20
*0402_short-p
H_PRDY#
PCH_XDP_PREQ#_R
32
BP27
R330
*0402_short-p
PCH_XDP_PRDY#_R
32
CFG_RCOMP
BT25
H_SKTOCC_N
R331
49.9_1%_04
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
CFG4
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
DEFENSIVE PULL DOWN SITE
CFG7
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
Title
Title
Title
[04]Processor 4/7-CLK/JTAG/MISC
[04]Processor 4/7-CLK/JTAG/MISC
[04]Processor 4/7-CLK/JTAG/MISC
3.3VA
9,24,26,27,30,48
1.05DX_VCCSTG
6,27,48
1.05_VCCST
6,26,47,48
Size
Size
Size
Document
Document
Document
Number
Number
Number
VDD3
24,25,27,30,34,36,37,40,42,43,44,48,50,51,52,53
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
VCCIO
2,6,43
Date :
Date :
Date :
Friday, March 02, 2018
Friday, March 02, 2018
Friday, March 02, 2018
2
Schematic Diagrams
1
reset
sequence
after
PCU
Reserved
configuration
lane.
Static
x16
Lane
D
Reserved
configuration
lane.
eDP
enable:
PCI
Express*
Bifurcation
PEG
Training:
Reserved
configuration
1.05DX_VCCSTG
R321
*51_04
R320
51_04
C
Sheet 4 of 60
CLOSE TO CPU
< 1.1"
3.3VA
Processor 3/6
R298
100K_04
B
A
R e v
R e v
R e v
6-71-N85J0-D01
6-71-N85J0-D01
6-71-N85J0-D01
D02B
D02B
D02B
Sheet
Sheet
Sheet
4
4
4
o f
o f
o f
63
63
63
1
Processor 3/6 B - 5
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