Power Sequence - Clevo N870EJ1 Service Manual

Power Sequence

5
N850EJ Timing for G3 to S0/M0 [Non-Deep Sx Platform]
BIOS P 2 A F S P
E C P 1 C
0 1 2 3 .. 30 ...... 100
VDD3
D
SLP_SUS#
257.86us
1.8VA
1.207ms
1.05VA
PWR_BTN#
2.7145ms
3.3VA
RSMRST
50.606ms
30.5215ms
DD_ON
883us
3.3V
3.518ms
VDD5
3.518ms
5V
226.525ms
SUSC#
VDDQ
2.5V
1.05_VCCST
C
SUSB#
DDR1.35V_PWRGD
VCCIO_EN
VCCIO
3.3VS
5VS
VCCIO_PWRGD
ALL_SYS_PWRGD
DDR_VTT_PG_CTRL
VTT_MEM
VCCST_PWRGD
VCORE_PG
PM_PCH_PWROK
VCCSA
B
SUSB#_C10#
1.05DX_VCCSTG
VCCSFR_OC
SYS_PWROK
PM_PWROK
PLT_RST#
H_PWRGD
VCORE
A
5
4 3
( tPCH01: VccRTC stable (@90% of full value) to assertion RTCRST# high and SRTCRST# high.
376.44ms
( tPCH03: VccPrimary stable (@95% of full value) to RSMRST# high >10ms )
1.57ms ( tCPU01: VDDQ ramped and stable to VccST_PWRGD assertion >1ms , 2.404ms )
( tCPU03 : VDDQ ramped and stable before VCCST stable < 25ms , 2.282ms )
1.915ms ( tPLT16 : VPP stable to VDDQ stable on power up > 30ms , -0.335ms )
This value is a suggested timing.
3.852ms ( tCPU00:VCCST ramped and stable to VccST_PWRGD assertion >1ms , 2.66506ms )
( tCPU04:VCCST must always ramp with or earlier then VCCSTG. VCCST >= VCCSTG at all times during ramp > 0ns , 14.082ms )
0 1 2 3 4 5 7
6 8 9 10 ........ 20 30 40 50 60 70 80 90 100 ........ 200
35.564us ( tPCH28: SLP_S3# assertion to SLP_S4# assertion >30us , 35us )
( tPCH29: SLP_S3# assertion to PCH_PWROK deassertion >0ms , 6.072ms )
2.766ms
2.766ms
3.84ms
1.181ms
1.262ms
( tPCH34 : All PCH Primary Rails should ramp up within this window. >80ms )
4.04ms
3.966ms ( tPLT04 : ALL_SYS_PWRGD assertion to PCH_PWROK This timing must be controlled on the platform
( tCPU18 : DDR_VTT_CNTL (was DDR_PG_CTL) assertion to DDR VTT
3.966ms
supplied ramped and stable while PLTRST = H (de-asserted). 0us < t < 35us , 18.043us )
3.966ms
3.974ms
( tCPU16 : VCCST_PWRGD assertion to PCH_PWROK assertion > 0ns , 2.098ms )
( tCPU19 : VccST_PWRGD assertion to DDR_VTT_CNTL (was DDR_PG_CTL) asserted. 0ns< t < 100ns , 66.2ns )
6.072ms
6.072ms ( tPCH33: PCH_PWROK high to PLTRST# de-assertion This timing is set by the PCH via Soft strap settings.
>99ms , 166ms )
6.162ms ( tCPU05 : VDDQ ramped and stable before VCCSA/VCCIO ramps > 100ns , 4.59ms/2.27ms )
( tCPU06 : VCCST ramped and stable before VCCSA/VCCIO ramps > 100ns , 6.148ms/3.826ms )
( tCPU07 : VCCSA ramped and stable before VCCIO stable Note: there is no timing requirement between )
16.9ns
( tCPU26 : CPU_C10_GATE# de-assertion to VCCSTG stable 10us < t < 65us , 14us
Note: CPU_C10_GATE# de-assertion to VCCST also needs to meet max 65us on cold boot )
14.096us
1.599ms
171.316ms
171.316ms
172.415ms
106.876ms
( tCPU09 :VCCSA stable before PROCPWRGD > 1ms , 100.708ms )
( tCPU10 : VCCIO stable before PROCPWRGD > 1ms , 103.03ms )
( tCPU11 : VCCPLL stable before PROCPWRGD > 1ms , 106.856ms )
( tCPU12 : VCCPLL_OC stable before PROCPWRGD > 1ms , 105.277ms )
193.665ms
4 3
2 1
>9ms )
> 1ms , 2.107ms )
CLEVO CLEVO CLEVO CLEVO CLEVO CLEVO
Title Title Title Title Title Title
[60]Power Sequencing [60]Power Sequencing [60]Power Sequencing [60]Power Sequencing [60]Power Sequencing [60]Power Sequencing
Size Size Size Size Size Size Document Number Document Number Document Number Document Number Document Number Document Number
Custom Custom Custom Custom Custom Custom 6-71-N85H0-D02B 6-71-N85H0-D02B 6-71-N85H0-D02B 6-71-N85H0-D02B 6-71-N85H0-D02B 6-71-N85H0-D02B
Date: Date: Date: Date: Date: Date: Friday, March 02, 2018 Friday, March 02, 2018 Friday, March 02, 2018 Friday, March 02, 2018 Friday, March 02, 2018 Friday, March 02, 2018 Sheet Sheet Sheet Sheet Sheet Sheet 61 60 60 61 61 60 o f o f o f o f o f o f
2 1
Schematic Diagrams
D
Sheet 60 of 60
Power Sequence
C
B
A
Re v Re v Re v Re v Re v Re v
D02A D02A D02A D02A D02A D02A
63 63 63 63 63 63
Power Sequence B - 61