Table of Contents
Advertisement
Chapter 1: Introduction
1-2
Chipset Overview
Built upon the functionality
and the capability of the E7320 (Lindenhurst-
VS)
chipset, the X6DVL-EG2 motherboard provides the performance and
feature set required for dual processor-based servers, with configuration
options optimized for communications, presentation, storage, computation or
database applications. The Intel E7320 (Lindenhurst-VS) chipset
consists
of the following components: the E7320 (Lindenhurst-VS) Memory Control-
ler Hub (MCH) and the I/O Controller Hub (6300ESB ICH).
The E7320 (Lindenhurst-VS) MCH supports single or dual Xeon EM64T (No-
cona) processors with Front Side Bus speeds of up to 800 MHz(*Note). Its
memory controller provides direct connection to two channels of registered
DDR2 400 with a marched system bus address and data bandwidths of up
to 6.4GB/s. The E7320 (Lindenhurst-VS) also supports the new PCI Ex-
press high speed serial I/O interface for superior I/O bandwidth. The MCH
provides configurable x8 PCI Express interfaces which may alternatively be
configured as two independent x4 PCI Express interfaces. These interfaces
support connection of the MCH to a variety of other bridges that are com-
pliant with the PCI Express Interface Specification, Rev. 1.0a.
The MCH
interfaces with the 6300ESB I/O Controller Hub
(6300ESB ICH) via Hub
Interface.
6300 ESB (Hance Rapids) ICH System Features
In addition to providing the I/O subsystem with access to the rest of the
system, the Hance Rapids ICH I/O Controller Hub
integrates many
I/O
functions.
The Hance Rapids ICH I/O Controller Hub integrates: 2-channel Ultra ATA/
100 Bus Master IDE Controller, two Serial ATA (SATA) Host Controllers,
SMBus 2.0 Controller, LPC/Flash BIOS Interface, PCI (66MHz) Interface, PCI
2.2 Interface and System Management Controller.
(*Notes: The CPU FSB speed is set at 800 MHz by the Manufacturer. Please
do not change the CPU FSB setting.)
1-9
Advertisement
Table of Contents
