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Figure 41. Processor and memory module layout: processor 3 and 4
Table 37. Processor and memory module layout: processor 3 and 4
Processor 3
1
DIMM 31-42
2
Processor 4
3
Table 38. Channel and slot information of DIMMs around a processor
Slot
0
Channel
Channel 2
DIMM number
1
(Processor 1)
DIMM number
13
(Processor 2)
DIMM number
25
(Processor 3)
DIMM number
37
(Processor 4)
Independent memory mode guidelines:
• Individual memory channels can run at different DIMM timings, but all channels must run at the same
interface frequency.
• Populate memory channel 0 first.
• Memory channel 1 is empty or identically populated as memory channel 0.
• Memory channel 2 is empty or identically populated as memory channel 1.
• In each memory channel, populate slot 0 first.
• If a memory channel has two DIMMs, populate the DIMM with a higher number of ranks in slot 0.
The independent memory mode DIMM population sequences for each supported processor configuration
are:
•
"Installation order: independent memory mode with two processors" on page 60
•
"Installation order: independent memory mode with four processors" on page 61
ThinkSystem SR850 Setup Guide
58
1
0
1
0
Channel 1
Channel 0
2
3
4
5
14
15
16
17
26
27
28
29
38
39
40
41
DIMM 43-48
4
DIMM 25-30
5
1
6
Processor
18
30
42
1
0
1
0
Channel 0
Channel 1
7
8
9
10
19
20
21
22
31
32
33
34
43
44
45
46
1
0
Channel 2
11
12
23
24
35
36
47
48
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