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E2 Design Changes
9. Added two 2:1 MUX's to support new HSEC ADC Connections.
MUX_SEL Signal
ADC1_MUX_SEL
ADC2_MUX_SEL
10. Updated ADC ESD Connections.
E1 ESD Pin
E1 Signal
U26.1
HSEC_ADC0_AIN0_P
U26.2
GND
U26.3
HSEC_ADC0_AIN0_N
U26.4
HSEC_ADC0_AIN1_N
U26.5
VDDA_IO_1V8
U26.6
HSEC_ADC0_AIN1_P
U27.1
HSEC_ADC0_AIN2_P
U27.2
GND
U27.3
HSEC_ADC0_AIN2_N
U27.4
HSEC_ADC1_AIN0_N
U27.5
VDDA_IO_1V8
U27.6
HSEC_ADC1_AIN0_P
U28.1
HSEC_ADC1_AIN1_P
U28.2
GND
U28.3
HSEC_ADC1_AIN1_N
U28.4
HSEC_ADC1_AIN2_N
U28.5
VDDA_IO_1V8
U28.6
HSEC_ADC1_AIN2_P
U29.1
HSEC_ADC2_AIN0_P
U29.2
GND
U29.3
HSEC_ADC2_AIN0_N
U29.4
HSEC_ADC2_AIN1_N
U29.5
VDDA_IO_1V8
U29.6
HSEC_ADC2_AIN1_P
U30.1
HSEC_ADC2_AIN2_P
U30.2
GND
U30.3
HSEC_ADC2_AIN2_N
U30.4
HSEC_ADC3_AIN0_N
56
AM263x Control Card Hardware User's Guide
Table A-8. E2 HSEC MUX Table
Condition
SEL Signal HIGH
SEL Signal LOW
SEL Signal HIGH
SEL Signal LOW
Table A-9. E2 ESD Connection Mapping
Copyright © 2023 Texas Instruments Incorporated
Function
Description
S1A->D1
route HSEC_ADC0_AIN0 to AM263
S2A->D2
route HSEC_ADC0_AIN1 to AM263
S1B->D1
route HSEC_DAC_OUT to AM263
S2B->D2
route HSEC_DAC_OUT to AM263
S1A->D1
route HSEC_ADC4_AIN0 to AM263
S2A->D2
route HSEC_ADC4_AIN1 to AM263
S1B->D1
route ADC_CAL0 to AM263
S2B->D2
route ADC_CAL0 to AM263
E2 ESD Pin
E2 Signal
U35.1
HSEC_ADC0_AIN0/DAC_OUT
U35.2
GND
U35.3
HSEC_ADC0_AIN1/DAC_OUT
U35.4
HSEC_ADC4_AIN0/ADC_CAL0
U35.5
VDDA_IO_3V3
U35.6
HSEC_ADC4_AIN1/ADC_CAL1
U36.1
HSEC_ADC1_AIN0
U36.2
GND
U36.3
HSEC_ADC1_AIN1
U36.4
HSEC_ADC0_AIN3
U36.5
VDDA_IO_3V3
U36.6
HSEC_ADC0_AIN2
U37.1
HSEC_ADC2_AIN0
U37.2
GND
U37.3
HSEC_ADC2_AIN1
U37.4
HSEC_ADC0_AIN5
U37.5
VDDA_IO_3V3
U37.6
HSEC_ADC0_AIN4
U38.1
HSEC_ADC3_AIN0
U38.2
GND
U38.3
HSEC_ADC3_AIN1
U38.4
HSEC_ADC3_AIN3
U38.5
VDDA_IO_3V3
U38.6
HSEC_ADC3_AIN2
U39.1
HSEC_ADC3_AIN4
U39.2
GND
U39.3
HSEC_ADC3_AIN5
U39.4
HSEC_ADC2_AIN3
SPRUJ09C – MARCH 2022 – REVISED FEBRUARY 2023
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